Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 223
PCI Controller—Intel® IXP42X product line and IXC1100 control plane processors
The IXP42X product line and IXC1100 control plane processors are a single-function,
Type 0 Configuration space when functioning as a PCI option. For detailed information
on the values to program the PCI Controller Configuration and Status Registers, see the
PCI Local Bus Specification, Rev.2.2.
The PCI Configuration Port Write Data (PCI_CRP_WDATA) Register is a 32-bit register
that is used to place the data that is to be written into the PCI Configuration Space.
The PCI Configuration Port Read Data (PCI_CRP_RDATA) Register is a 32-bit register
that is used to capture the data that is returned from the PCI Configuration Space. The
PCI Configuration Port Address/Command/Byte Enables (PCI_CRP_AD_CBE) Register is
a register that provides the address, byte enables, and control for the read and write
access to the PCI Configuration Space from the internal side of the IXP42X product line
and IXC1100 control plane processors.
• Bits 23:20 of the PCI Configuration Port Address/Command/Byte Enables
(PCI_CRP_AD_CBE) Register specify the byte enables for the access to the PCI
Configuration Space
These bits directly correspond to the four - byte field associated with the PCI
Configuration Port Write Data (PCI_CRP_WDATA) Register. Table 100 on page 224
shows the mapping of the byte enables of the PCI Configuration Port Address/
Command/Byte Enables (PCI_CRP_AD_CBE) Register to the byte lane fields of the
PCI Configuration Port Write Data (PCI_CRP_WDATA) Register.
• Bits 7:2 of the PCI Configuration Port Address/Command/Byte Enables
(PCI_CRP_AD_CBE) Register specify the address for the register access within the
64 32-bit Word PCI Configuration Space.
The 64 32-bit Word PCI Configuration Space is shown in Table101 on page 225.
• Bits 19:16 of the PCI Configuration Port Address/Command/Byte Enables
(PCI_CRP_AD_CBE) Register specify the command to execute on the PCI
Configuration Space. The only two commands currently defined are read and write.
Table102 on page 225 shows valid command codes for accessing the PCI
Configuration Space. When a read command is written into the command field of
the PCI Configuration Port Address/Command/Byte Enables (PCI_CRP_AD_CBE)
Register along with the appropriate address of the PCI Configuration register to be
accessed, the data from the address requested will be returned to the PCI
Configuration Port Read Data (PCI_CRP_RDATA) Register.
A master on the AHB bus can then read the PCI Configuration Port Read Data
(PCI_CRP_RDATA) Register. For example:
1. PCI_CRP_AD_CBE is written with hexadecimal 0x00300004, which causes the
contents of the PCI Control Register/Status Register (PCI_SRCR) to be written into
the PCI_CRP_RDATA register.
Note that bits 23:20 are set to hexadecimal 3. For read accesses, byte-enables are
ignored. Bits 19:16 are set to hexadecimal 0, which denotes a read command. Bits
7:0 are set to hexadecimal 04.
2. PCI_CRP_RDATA is read by the AHB master that requested the PCI_SRCR to be
returned to the PCI_CRP_RDATA register.
When a write to the PCI Configuration Space is desired, the AHB master requesting the
write must update the PCI Configuration Port Write Data (PCI_CRP_WDATA) Register
with the data that is to be written to the PCI Configuration Register. Once the PCI
Configuration Port Write Data (PCI_CRP_WDATA) Register has been updated, a write
command is written into the command field of the PCI Configuration Port Address/
Command/Byte Enables (PCI_CRP_AD_CBE) Register along with the appropriate byte
enables and address of the PCI Configuration register to be accesses.
The data contained in the PCI Configuration Port Write Data (PCI_CRP_WDATA)
Register will be written to the PCI Configuration Register specified by the address and
byte enables contained in the PCI Configuration Port Address/Command/Byte Enables
(PCI_CRP_AD_CBE) Register. For Example: