Intel® IXP42X product line and IXC1100 control plane processors—Interrupt Controller
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
398 Order Number: 252480-006US
13.0 Interrupt Controller
The Interrupt Controller takes as inputs 32 individual interrupts. These 32 individual
interrupts originate either from the Intel® IXP42X Product Line of Network Processors
and IXC1100 Control Plane Processor internal blocks or from 14 dedicated GPIO pins.
The highest priority interrupt is bit [0] assigned to the WAN/Voice NPE and the lowest
priority interrupt is bit [31] assigned to a Software Interrupt. The Intel® IXP42X
product line and IXC1100 control plane processors’ Interrupt Controller is implemented
to expand the interrupt capabilities of the Intel XScale® Processor.
The Intel XScale processor only has a fast interrupt (FIQ) and a maskable interrupt
(IRQ). The interrupts collected by the Interrupt Controller are combined and configured
to be an FIQ interrupt or an IRQ. The FIQ signal going to the Intel XScale processor will
be set when any of the interrupts assigned to be an FIQ become set. The IRQ signal
going to the Intel XScale processor will be set when any of the interrupts assigned to
be an IRQ are set.
The Interrupt Controller consists of:
The Interrupt Controller has no concept of setting or clearing any interrupts. The intent
of the Interrupt Controller is to collect and prioritize the received interrupts from other
sources. In order to set an interrupt, the device connected to the assigned interrupt
line must assert the interrupt.
Clearing of the interrupt must be made at the device that caused the interrupt. If the
interrupt is not cleared at the device that asserted the interrupt, the interrupt will be
service again.

13.1 Interrupt Priority

Selecting the priority of interrupts is done through the assignment of the interrupt
priority register and natural interrupt priority assigned by interrupt number. As
described, the interrupts follow a natural priority. The interrupt connected to interrupt 0
(WAN/Voice NPE) has the highest priority and the interrupt connected to interrupt 31
(Software Interrupt 1) has the lowest priority.
In addition to the natural priority the lowest eight interrupts, interrupt 0 to interrupt 7,
can be assigned a priority value by writing the interrupt priority register (INTR_PRTY).
The interrupt priority register is broken up into eight 3-bit registers.
Bits 0 through 2 of the interrupt priority register assign a priority value to interrupt 0
(WAN/Voice NPE). Bits 3 through 5 of the interrupt priority register assign a priority to
interrupt 1 (Ethernet A NPE). The interrupt priority values are assigned in a similar
• A 32-bit interrupt status register • A 32-bit interrupt enable register
• A 32-bit interrupt select register • A 32-bit IRQ status register
• A 32-bit FIQ status register • A 32-bit interrupt priority register
• A 6-bit IRQ highest priority register • A 6-bit FIQ highest priority register