Intel IXC1100, IXP42X 20.3.1 Boundary Scan Register, 20.3.2 Instruction Register, 20.3.3 JTAG Device ID Register

Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 555
JTAG Interface—Intel® IXP42X product line and IXC1100 control plane processors
Data is received, from JTG_TDI, through a shift register and exits through JTG_TDO
one bit at a time on the rising edge of JTG_TCK. The data can then be copied (parallel
loaded) into the associated read/write register when the data-register_write command
is loaded in the JTAG Instruction Register and the TAP controller enters the Update-DR
state.
Finally, when the TAP controller enters the Capture-DR state and the JTAG Instruction
Register has either data-register_write or data-register_read in it, the read/write
register data is copied into the associated shift register and will be out to TDO when the
TAP controller enters the Shift-DR state.
20.3.1 Boundary Scan Register
The Boundary Scan Register is a shift register, comprised of boundary-scan cells in the
pads. Power, ground, and JTAG pins are not equipped with boundary-scan cells. The
Boundary Scan Register is fully IEEE 1149.1-compliant. This N-bit register is connected
between TDI and TDO when BS_EXTEST, BS_SAMPLE/PRELOAD, or the BS_CLAMP
instructions are selected. The Boundary Scan Register is used for capturing signal-pin
data on the input pins, forcing fixed values on the output signal pins and selecting the
direction and drive characteristics (a logic value or high impedance) of the bidirectional
and three-state signal pins.
Also, if BS_SAMPLE/PRELOAD or BS_EXTEST are loaded into the JTAG Instruction
Register, the TAP controller states SHIFT-DR, CAPTURE-DR, and UPDATE-DR are used
to conduct the boundary-scan testing. SHIFT-DR will now control the shift-select
multiplexer in the boundary scan logic of the pads, CAPTURE-DR will clock the
boundary scan shift register, and UPDATE-DR will drive the boundary scan data to
either the internal logic of the IXP42X product line and IXC1100 control plane
processors or to a pin depending on the direction of the pin (input or output).
20.3.2 Instruction Register
The JTAG Instruction Register, that resides in the Intel XScale processor JTAG unit,
behaves similar to the Data Registers. No instruction is required to load the JTAG
Instruction Register and the pertinent, relative TAP controller states are Shift-IR,
Capture-IR, and Update-IR.
The Intel XScale processor provides the Test Logic Unit with the instruction status so
that the Test Logic Unit can decode the current instruction and act accordingly.
20.3.3 JTAG Device ID Register
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Table 175. JTAG Device Register Values
JTAG ID
(32-Bit Value) Speed (MHz)
0x19274013 533
0x19275013 400
0x19277013 266