Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 63
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors
caching is specified for that area of memory. If the cache does not contain the
requested data, the access ‘misses’ the cache, and the sequence of events that follows
depends on the configuration of the cache, the configuration of the MMU and the page
attributes, which are described in “Cacheability” on page 63.
The data/mini-data cache is still accessed even though it is disabled. If a load hits the
cache it will return the requested data to the destination register. If a store hits the
cache, the data is written into the cache. Any access that misses the cache will not
allocate a line in the cache when it’s disabled, even if the MMU is enabled and the
memory region’s cacheability attribute is set.
3.4.2 Cacheability
Data at a specified address is cacheable given the following:
• the MMU is enabled
• the cacheable attribute is set in the descriptor for the accessed address
• and the data/mini-data cache is enabled
The following sequence of events occurs when a cacheable (see “Cacheability” on
page 63) load operation misses the cache:
1. The fill buffer is checked to see if an outstanding fill request already exists for that
line.
If so, the current request is placed in the pending buffer and waits until the
previously requested fill completes, after which it accesses the cache again, to
obtain the request data and returns it to the destination register.
If there is no outstanding fill request for that line, the current load request is placed
in the fill buffer and a 32-byte external memory read request is made. If the
pending buffer or fill buffer is full, the Intel XScale processor will stall until an entry
is available.
2. A line is allocated in the cache to receive the 32-bytes of fill data. The line selected
is determined by the round-robin pointer. (See “Cacheability” on page63.) The line
chosen may contain a valid line previously allocated in the cache. In this case both
dirty bits are examined and if set, the four words associated with a dirty bit that’s
asserted will be written back to external memory as a four word burst operation.
3. When the data requested by the load is returned from external memory, it is
immediately sent to the destination register specified by the load. A system that
returns the requested data back first, with respect to the other bytes of the line,
will obtain the best performance.
4. As data returns from external memory it is written into the cache in the previously
allocated line.
A load operation that misses the cache and is NOT cacheable makes a request from
external memory for the exact data size of the original load request. For example,
LDRH requests exactly two bytes from external memory, LDR requests 4 bytes from
external memory, etc. This request is placed in the fill buffer until, the data is returned
from external memory, which is then forwarded back to the destination register(s).
A write operation that misses the cache will request a 32-byte cache line from external
memory if the access is cacheable and write allocation is specified in the page. In this
case the following sequence of events occur:
1. The fill buffer is checked to see if an outstanding fill request already exists for that
line.
If so, the current request is placed in the pending buffer and waits until the
previously requested fill completes, after which it writes its data into the recently
allocated cache line.