Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 423
Ethernet MAC A—Intel® IXP42X product line and IXC1100 control plane processors
period will be the number of transmit clock cycles specified by the 8-bit Transmit
Deferral Register minus three transmit clock cycles. The Single Transmit Deferral
parameter specifies the Inter Frame Gap.
In the two-part deferral process the deferral period is defined using the Transmit Two
Part Deferral Parameters 1 Register (TX2PARTDEFPARS1) and Transmit Two Part
Deferral Parameters 2 Register (TX2PARTDEFPARS2). To ensure fair access to the
medium, the values specified in these two registers, when added together, should not
be less than the minimum Inter Frame Gap.
The Transmit Two Part Deferral Parameters 1 Register is typically set to two thirds of
the Inter Frame Gap, and the Transmit Two Part Deferral Parameters 2 Register is
typically set to the remaining one third.
If the transmit engine has a frame ready to transmit and two-part transmit deferral is
selected, the transmit engine will wait for the medium to go silent and then wait for the
time period specified in the Transmit Two Part Deferral Parameters 1 Register. If the
medium is not silent during this first part of the deferral then the deferral counter is
reset. If the medium is silent during the first part of the deferral then the transmit
engine continues to wait for the time period specified in the Transmit Two Part Deferral
Parameters 2 Register.
When the MII interface of the IXP42X product line and IXC1100 control plane
processors is configured in full-duplex mode of operation, the two-part transmit
deferral parameters and the back-off times will not be utilized for data transmission.
For more information on Deference, refer to IEEE 802.3, Section 4.2.3.2.1.
15.1.5 Receiving Ethernet Frames with MII Interfaces
When data is received using the MII interface, the Receive engine will be used to
convert the data from 4-bit nibbles into 8-bit bytes. The receive interface will then send
the data from a byte to 32-bit word converter. The 32-bit word will be written into the
256-byte receive FIFO.
A flag will be generated to inform the NPE that the receive FIFO has new data to be
removed after the Threshold for Partial Full/Empty value has been reached. The
Receive Engine implements the following functions:
• Enable/Disable the receive engine
• Implements uni-cast/multi-cast/broadcast, single-address filtering
• Checks for runt frames
• Checks for valid length/type fields
• Removes padded bits added to frames
• Implements the Frame-Check Sequence Algorithm
When new receive data is detected, the Receive Engine will look to see if the address
filtering checks are enabled. If the address filtering checks are enable by setting bit 5 of
the Receive Control Register 1 (RXCTRL1) to logic 1, the Receive Engine will obtain the
destination address from the received frame, check the destination address against the
address filtering parameters, and pass the frame to the 8-bit to 32-bit framing engine,
if the test passed.
The Receive Engine is capable of filtering broadcast frames, multi-cast frames, and uni-
cast frames. The frame filtering for multi-cast frames and uni-cast frames is controlled
by registers Address Mask Register (ADDRMASK), the Address Register (ADDR), and
the Uni-Cast Register (UNIADDR).