Intel IXC1100, IXP42X 10.2.2 Setting Data Bits/Stop Bits/Parity

Intel® IXP42X product line and IXC1100 control plane processors—Universal Asynchronous
Receiver Transceiver (UART)
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
336 Order Number: 252480-006US
10.2.2 Setting Data Bits/Stop Bits/Parity
The Line Control Register (LCR) is an 8-bit register that enables the system
programmer to specify the format of the asynchronous data communications exchange.
The serial data format consists of a start bit (logic 0), five to eight data bits, an optional
parity bit, and one or two stop bits (logic 1). The Line Control Register also contains a
bits used for accessing the Divisor Latch Registers and causing a UART break condition.
The programmer also has the ability to read the contents of the Line Control Register.
The 8-bit Line Control Register is broken up into seven smaller registers
The Divisor-Latch Access Bit must be set to logic 1 to access the Divisor Latch Registers
of the baud-rate generator. When the Divisor-Latch Access Bit is set to logic 0,
accessing the same addresses as defined for accessing the Divisor Latch Registers will
allow access to the Receiver Buffer, the Transmit Holding Register, or the Interrupt
Enable Register.
The Set-Break Control Bit causes a UART break condition to be transmitted to the
receiving UART. When Set-Break Control Bit is set to logic 1, the serial output data
(TXD) is forced to the spacing or logic 0 state and remains in the spacing state until
Set-Break Control Bit is set to logic 0. When the Set-Break Control Bit is set to logic 0,
the serial output data is transmitted normally from the transmit-holding register. The
Set-Break feature enables the processor to alert a terminal in a computer
communications system.
The Sticky-Parity Bit (STKYP) is used to transmit the complement of the Even-Parity
Select when parity is enabled. When the Parity-Enable Bit and Sticky-Parity Bit are logic
1, the bit that is transmitted — in the parity bit location of the serial output data stream
— is the complement of the Even-Parity Select Bit.
For example, the Even-Parity Select Bit is logic 0 and the parity-bit location of the serial
output data stream will be transmitted as logic 1. When the Sticky-Parity Bit and Parity-
Enable bits are logic 1, the receiver logic compares the parity bit that is received — in
the parity bit location of the serial data input stream — with the complement of the
Even-Parity Select Bit.
If the values being compared are not equal, the receiver sets the Parity-Error Bit in
Line-Status Register and causes an interrupt error if Line-Status Interrupts are
enabled.
If the Even-Parity Select Bit is logic 0, the receiver expects the bit received at the
parity-bit location of the serial data input stream to be logic 1. If the parity bit received
is logic 0, the parity-error bit is set to logic 1. By forcing the bit value at the parity bit
location, rather than calculating a parity value, a system with a master transmitter and
multiple receivers can identify some transmitted characters as receiver addresses and
the rest of the characters as UART data.
If Parity enable is set to logic 0, Sticky Parity will be ignored.
• Divisor-Latch Access
Bit • Set-Break Bit • Sticky-Parity Bit
• Even-Parity Select Bit • Parity-Enable Bit • Stop-Bits Bit
•Word-Length Select
Bits