Intel® IXP42X product line and IXC1100 control plane processors—Overview of Product Line
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
42 Order Number: 252480-006US
2.12 Universal Asynchronous Receiver Transceiver
The UART interfaces are 16550-compliant UARTs with the exception of transmit and
receive buffers. Transmit and receive buffers are 64bytes-deep versus the 16 bytes
required by the 16550 UART specification.
The interface can be configured to support speeds from 1,200 baud to 921Kbaud. The
interface support configurations of:
• Five, six, seven, or eight data-bit transfers
• One or two stop bits
• Even, odd, or no parity
The request-to-send (RTS_N) and clear-to-send (CTS_N) modem control signals also
are available with the interface for hardware flow control.
For more information on the UART interfaces, see Section 10.0, “Universal
Asynchronous Receiver Transceiver (UART)” on page332.
2.13 GPIO
There are 16 GPIO pins supported by the IXP42X product line and IXC1100 control
plane processors. GPIO pins 0 through 13 can be configured to be general-purpose
input or general-purpose output. Additionally, GPIO pins 0 through 12 can be
configured to be an interrupt input.
GPIO Pin 14 can be configured similar to GPIO pin 13 or as a clock output. The output-
clock configuration can be set at various speeds, up to 33.33 MHz, with various duty
cycles. GPIO Pin 14 is configured as an input, upon reset.
GPIO Pin 15 can be configured similar to GPIO pin 13 or as a clock output. The output-
clock configuration can be set at various speeds, up to 33.33 MHz, with various duty
cycles. GPIO Pin 15 is configured as a clock output, upon reset. GPIO Pin 15 can be
used to clock the expansion interface, after reset.
For more information on the GPIO pins, see Section 12.0, “General Purpose Input/
Output (GPIO)” on page 386.
2.14 Interrupt Controller
The IXP42X product line and IXC1100 control plane processors consist of 32 interrupt
sources to allow an extension of the Intel XScale processor’s FIQ and IRQ interrupt
sources. These sources can originate from external GPIO pins or internal peripheral
interfaces.
The interrupt controller can configure each interrupt source as FIQ, IRQ, or disabled.
The interrupt sources tied to Interrupt 0 to 7 can be prioritized. The remaining
interrupts are prioritized in ascending order. (For example, 8 has a higher priority than
9.)
For more information on the interrupt controller, see Section 13.0, “Interrupt
Controller” on page 398.
2.15 Timers
The IXP42X product line and IXC1100 control plane processors consists of four internal
timers operating at 66.66 MHz (which is 2 * OSC_IN input pin.) to allow task
scheduling and prevent software lock-ups. The device has four 32-bit counters: