Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 37
Overview of Product Line—Intel® IXP42X product line and IXC1100 control plane processors
2.1.1.3 Memory Management
The Intel XScale processor implements the Memory Management Unit (MMU)
Architecture specified in the ARM Architecture Reference Manual. The MMU provides
access protection and virtual-to-physical address translation.
The MMU Architecture also specifies the caching policies for the instruction cache and
data cache. These policies are specified as page attributes and include:
• Identifying code as cacheable or non-cacheable
• Selecting between the mini-data cache or data cache
• Write-back or write-through data caching
• Enabling data-write allocation policy
• Enabling the write buffer to coalesce stores to external memory
For more details, see Section 3.1, “Memory Management Unit” on page 44.
2.1.1.4 Instruction Cache
The Intel XScale processor comes with a 32-Kbyte instruction cache. The instruction
cache is 32-way set associative and has a line size of 32 bytes. All requests that “miss”
the instruction cache generate a 32-byte read request to external memory. A
mechanism to lock critical code within the cache also is provided.
For more details, see “Instruction Cache” on page 52.
2.1.1.5 Branch Target Buffer
The Intel XScale processor provides a Branch Target Buffer (BTB) to predict the
outcome of branch-type instructions. It provides storage for the target address of
branch type instructions and predicts the next address to present to the instruction
cache, when the current instruction address is that of a branch.
The BTB holds 128 entries. For more details, see “Branch Target Buffer” on page58.
2.1.1.6 Data Cache
The Intel XScale processor comes with a 32-Kbyte data cache. Besides the main data
cache, a mini-data cache is provided whose size is 1/16th the main data cache. (A
32-Kbyte main data cache has a 2-Kbyte mini-data cache.)
The main data cache is 32-way set associative and the mini-data cache is two-way set
associative. Each cache has a line size of 32 bytes and supports write-through or write-
back caching.
The data/mini-data cache is controlled by page attributes defined in the MMU
Architecture and by coprocessor 15.
For more details, see “Data Cache” on page 60.
The Intel XScale processor allows applications to reconfigure a portion of the data
cache as data RAM. Software may place special tables or frequently used variables in
this RAM. For more information on this, see “Reconfiguring the Data Cache as Data
RAM” on page 68.