Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 9
—Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
8.9 Register Descriptions.......................................................................................319
8.9.1 Timing and Control Registers for Chip Select 0......................................... 319
8.9.2 Timing and Control Registers for Chip Select 1......................................... 319
8.9.3 Timing and Control Registers for Chip Select 2......................................... 320
8.9.4 Timing and Control Registers for Chip Select 3......................................... 320
8.9.5 Timing and Control Registers for Chip Select 4......................................... 320
8.9.6 Timing and Control Registers for Chip Select 5......................................... 321
8.9.7 Timing and Control Registers for Chip Select 6......................................... 321
8.9.8 Timing and Control Registers for Chip Select 7......................................... 321
8.9.9 Configuration Register 0........................................................................322
8.9.9.1 User-Configurable Field............................................................324
8.9.10 Configuration Register 1........................................................................324
8.10 Expansion Bus Controller Performance............................................................... 326
9.0 AHB/APB Bridge .................................................................................................... 328
10.0 Universal Asynchronous Receiver Transceiver (UART) ...........................................332
10.1 High Speed UART............................................................................................333
10.2 Configuring the UART.......................................................................................335
10.2.1 Setting the Baud Rate...........................................................................335
10.2.2 Setting Data Bits/Stop Bits/Parity........................................................... 336
10.2.3 Using the Modem Control Signals ...........................................................338
10.2.4 UART Interrupts...................................................................................339
10.3 Transmitting and Receiving UART Data...............................................................342
10.4 Register Descriptions.......................................................................................344
10.4.1 Receive Buffer Register.........................................................................345
10.4.2 Transmit Holding Register .....................................................................345
10.4.3 Divisor Latch Low Register.....................................................................346
10.4.4 Divisor Latch High Register....................................................................346
10.4.5 Interrupt Enable Register...................................................................... 346
10.4.6 Interrupt Identification Register .............................................................347
10.4.7 FIFO Control Register............................................................................349
10.4.8 Line Control Register ............................................................................350
10.4.9 Modem Control Register........................................................................352
10.4.10Line Status Register..............................................................................353
10.4.11Modem Status Register .........................................................................354
10.4.12Scratch-Pad Register ............................................................................355
10.4.13Infrared Selection Register .................................................................... 356
10.5 Console UART.................................................................................................357
10.5.1 Register Description..............................................................................357
10.5.1.1 Receive Buffer Register............................................................ 358
10.5.1.2 Transmit Holding Register ........................................................358
10.5.1.3 Divisor Latch Low Register .......................................................359
10.5.1.4 Divisor Latch High Register ......................................................359
10.5.1.5 Interrupt Enable Register .........................................................360
10.5.1.6 Interrupt Identification Register ................................................360
10.5.1.7 FIFO Control Register ..............................................................362
10.5.1.8 Line Control Register ...............................................................363
10.5.1.9 Modem Control Register........................................................... 365
10.5.1.10Line Status Register................................................................366
10.5.1.11Modem Status Register............................................................367
10.5.1.12Scratch-Pad Register...............................................................368
10.5.1.13Infrared Selection Register.......................................................369
11.0 Internal Bus Performance Monitoring Unit (IBPMU) .............................................. 372
11.1 Initializing the IBPMU.......................................................................................372
11.2 Using the IBPMU.............................................................................................373