Intel IXC1100, IXP42X 3.10.2.3 Main Execution Pipeline

Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 171
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors
3.10.2.2.2 Pipeline Stalls
The progress of an instruction can stall anywhere in the pipeline. Several pipe stages
may stall for various reasons. It is important to understand when and how hazards
occur in the IXP42X product line and IXC1100 control plane processors’ pipeline.
Performance degradation can be significant if care is not taken to minimize pipeline
stalls.
3.10.2.3 Main Execution Pipeline
3.10.2.3.1 F1 / F2 (Instruction Fetch) Pipe Stages
The job of the instruction fetch stages F1 and F2 is to present the next instruction to be
executed to the ID stage. Several important functional units reside within the F1 and F2
stages, including:
• Branch Target Buffer (BTB)
• Instruction Fetch Unit (IFU)
An understanding of the BTB (See “Branch Target Buffer” on page58) and IFU are
important for performance considerations. A summary of operation is provided here so
that the reader may understand its role in the F1 pipe stage.
• Branch Target Buffer (BTB)
The BTB predicts the outcome of branch type instructions. Once a branch type
instruction reaches the X1 pipe stage, its target address is known. If this address is
different from the address that the BTB predicted, the pipeline is flushed, execution
starts at the new target address, and the branch’s history is updated in the BTB.
• Instruction Fetch Unit (IFU)
The IFU is responsible for delivering instructions to the instruction decode (ID) pipe
stage. One instruction word is delivered each cycle (if possible) to the ID. The
instruction could come from one of two sources: instruction cache or fetch buffers.
3.10.2.3.2 ID (Instruction Decode) Pipe Stage
The ID pipe stage accepts an instruction word from the IFU and sends register decode
information to the RF pipe stage. The ID is able to accept a new instruction word from
the IFU on every clock cycle in which there is no stall. The ID pipe stage is responsible
for:
• General instruction decoding (extracting the op code, operand addresses,
destination addresses and the offset).
• Detecting undefined instructions and generating an exception.
• Dynamic expansion of complex instructions into sequence of simple instructions.
Complex instructions are defined as ones that take more than one clock cycle to
issue, such as LDM, STM, and SWP.
3.10.2.3.3 RF (Register File / Shifter) Pipe Stage
The main function of the RF pipe stage is to read and write to the register file unit, or
RFU. It provides source data to:
•EX for ALU operations
• MAC for multiply operations
• Data Cache for memory writes
• Coprocessor interface