Intel IXC1100, IXP42X 3.10.4.2 Data and Mini Cache

Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 181
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors
• Interrupt handlers
• Real time clock handlers
• OS critical code
• Time critical application code
The disadvantage to locking code into the cache is that it reduces the cache size for the
rest of the program. How much code to lock is very application dependent and requires
experimentation to optimize.
Code placed into the instruction cache should be aligned on a 1,024-byte boundary and
placed sequentially together as tightly as possible so as not to waste precious memory
space. Making the code sequential also insures even distribution across all cache ways.
Though it is possible to choose randomly located functions for cache locking, this
approach runs the risk of landing multiple cache ways in one set and few or none in
another set. This distribution unevenness can lead to excessive thrashing of the Data
and Mini Caches.
3.10.4.2 Data and Mini Cache
The IXP42X product line and IXC1100 control plane processors allow the user to define
memory regions whose cache policies can be set by the user (see “Cacheability” on
page 63). Supported policies and configurations are:
• Non Cacheable with no coalescing of memory writes.
• Non Cacheable with coalescing of memory writes.
• Mini-Data cache with write coalescing, read allocate, and write-back caching.
• Mini-Data cache with write coalescing, read allocate, and write-through caching.
• Mini-Data cache with write coalescing, read-write allocate, and write-back caching.
• Data cache with write coalescing, read allocate, and write-back caching.
• Data cache with write coalescing, read allocate, and write-through caching.
• Data cache with write coalescing, read-write allocate, and write-back caching.
To support allocating variables to these various memory regions, the tool chain
(compiler, assembler, linker and debugger), must implement named sections.
The performance of your application code depends on what cache policy you are using
for data objects. A description of when to use a particular policy is described below.
The IXP42X product line and IXC1100 control plane processors allow dynamic
modification of the cache policies at run time, however, the operation is requires
considerable processing time and therefore should not be used by applications.
If the application is running under an OS, then the OS may restrict you from using
certain cache policies.
3.10.4.2.1 Non-Cacheable Regions
It is recommended that non-cache memory (X=0, C=0, and B=0) be used only if
necessary as is often necessary for I/O devices. Accessing non-cacheable memory is
likely to cause the processor to stall frequently due to the long latency of memory
reads.