Intel IXC1100, IXP42X - page 18

Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor—
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
18 Order Number: 252480-006US
35 Initiated PCI TYPE 0 Configuration Read Cycle............................................................227
36 Initiated PCI Type-0 Configuration Write Cycle ...........................................................228
37 Initiated PCI Type-1 Configuration Read Cycle............................................................228
38 Initiated PCI Type-1 Configuration Write Cycle ...........................................................229
39 Initiated PCI Memory Read Cycle..............................................................................230
40 Initiated PCI Memory Write Cycle..............................................................................231
41 Initiated PCI I/O Read Cycle ....................................................................................231
42 Initiated PCI I/O Write Cycle....................................................................................232
43 Initiated PCI Burst Memory Read Cycle......................................................................233
44 Initiated PCI Burst Memory Write Cycle.....................................................................234
45 AHB to PCI DMA Transfer Byte Lane Swapping...........................................................236
46 PCI to AHB DMA Transfer Byte Lane Swapping...........................................................236
47 Byte Lane Routing During PCI Target Accesses of the AHB –
AHB Configured as a Big-Endian Bus.........................................................................243
48 Byte Lane Routing During PCI Target Accesses of the AHB –
AHB Configured as a Little-Endian Bus.......................................................................244
49 Byte Lane Routing During AHB Memory Mapped Accesses of the PCI Bus –
AHB Configured as a Big-Endian Bus.........................................................................245
50 Byte Lane Routing During AHB Memory Mapped Accesses of the PCI Bus –
AHB configured as a Little-Endian Bus.......................................................................246
51 Byte Lane Routing During DMA Transfers...................................................................247
52 Byte Lane Routing During Configuration and Status Register Accesses......... ..................248
53 8-, 16-, 32-, 64- or 128-Mbyte — One-Bank SDRAM Interface Configuration.................. 277
54 64-, 128- or 256-Mbyte — Two-Bank SDRAM Interface Configuration................. .. .. .. .... . 278
55 SDRAM Read Example (CAS Latency of 2 Cycles)........................................................285
56 SDRAM Shared South AHB and North AHB Access.......................................................286
57 SDRAM Write Example............................................................................................287
58 Chip Select Address Allocation..................................................................................295
59 Expansion Bus Memory Sizing..................................................................................295
60 Expansion Bus Peripheral Connection........................................................................297
61 I/O Wait Normal Phase Timing .................................................................................302
62 I/O Wait Extended Phase Timing...............................................................................303
63 Expansion-Bus Write (Intel® Multiplexed Mode)..........................................................305
64 Expansion-Bus Read (Intel® Multiplexed Mode)..........................................................306
65 Expansion-Bus Write (Intel® Simplex Write Mode)......................................................307
66 Expansion-Bus Read (Intel® Simplex Mode)...............................................................308
67 Expansion-Bus Write (Motorola* Multiplexed Mode).....................................................309
68 Expansion-Bus Read (Motorola* Multiplexed Mode).....................................................310
69 Expansion-Bus Write (Motorola* Simplex Mode).........................................................311
70 Expansion-Bus Read (Motorola* Simplex Mode)..........................................................312
71 Expansion-Bus Write (TI* HPI-8 Mode)......................................................................313
72 Expansion-Bus Read (TI* HPI-8 Mode)......................................................................314
73 Expansion-Bus Write (TI* HPI-16 Multiplexed Mode)...................................................315
74 Expansion-Bus Read (TI* HPI-16 Multiplexed Mode)....................................................316
75 Expansion-Bus Write (TI* HPI-16 Simplex Mode)........................................................317
76 Expansion-Bus Read (TI* HPI-16 Simplex Mode)........................................................318
77 APB Interface.........................................................................................................329
78 UART Timing Diagram.............................................................................................333
79 UART Block Diagram...............................................................................................334
80 Multiple Ethernet PHYS Connected to Processor..........................................................407
81 Ethernet Coprocessor Interface................................................................................407
82 MDIO Write .................................................................................... .. .. ...................410
83 MDIO Read............................................................................................................410
84 Tx Frame-Sync Example (Presuming an Offset of 0)....................................................444
85 Rx Frame-Sync Example (Presuming Zero Offset).......................................................444