Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor—
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
6Order Number: 252480-006US
3.9.1 Interrupt Latency..................................................................................159
3.9.2 Branch Prediction..................................................................................160
3.9.3 Addressing Modes.................................................................................160
3.9.4 Instruction Latencies.............................................................................160
3.9.4.1 Performance Terms.................................................................160
3.9.4.2 Branch Instruction Timings.......................................................162
3.9.4.3 Data Processing Instruction Timings...........................................162
3.9.4.4 Multiply Instruction Timings......................................................163
3.9.4.5 Saturated Arithmetic Instructions..............................................165
3.9.4.6 Status Register Access Instructions............................................165
3.9.4.7 Load/Store Instructions............................................................165
3.9.4.8 Semaphore Instructions...........................................................166
3.9.4.9 Coprocessor Instructions..........................................................166
3.9.4.10 Miscellaneous Instruction Timing...............................................167
3.9.4.11 Thumb Instructions .................................................................167
3.10 Optimization Guide ..........................................................................................167
3.10.1 Introduction.........................................................................................167
3.10.1.1 About This Section ..................................................................168
3.10.2 Processors’ Pipeline...............................................................................168
3.10.2.1 General Pipeline Characteristics.................................................168
3.10.2.2 Instruction Flow Through the Pipeline.........................................170
3.10.2.3 Main Execution Pipeline............................................................171
3.10.2.4 Memory Pipeline......................................................................172
3.10.2.5 Multiply/Multiply Accumulate (MAC) Pipeline ............................... 173
3.10.3 Basic Optimizations...............................................................................173
3.10.3.1 Conditional Instructions ...........................................................173
3.10.3.2 Bit Field Manipulation...............................................................178
3.10.3.3 Optimizing the Use of Immediate Values ....................................178
3.10.3.4 Optimizing Integer Multiply and Divide.......................................178
3.10.3.5 Effective Use of Addressing Modes.............................................179
3.10.4 Cache and Prefetch Optimizations ...........................................................180
3.10.4.1 Instruction Cache....................................................................180
3.10.4.2 Data and Mini Cache................................................................181
3.10.4.3 Cache Considerations...............................................................184
3.10.4.4 Prefetch Considerations............................................................185
3.10.5 Instruction Scheduling...........................................................................191
3.10.5.1 Scheduling Loads....................................................................191
3.10.5.2 Scheduling Data Processing Instructions.....................................195
3.10.5.3 Scheduling Multiply Instructions................................................196
3.10.5.4 Scheduling SWP and SWPB Instructions..................................... 197
3.10.5.5 Scheduling the MRA and MAR Instructions (MRRC/MCRR)............. 197
3.10.5.6 Scheduling the MIA and MIAPH Instructions................................198
3.10.5.7 Scheduling MRS and MSR Instructions........................................198
3.10.5.8 Scheduling CP15 Coprocessor Instructions..................................199
3.10.6 Optimizing C Libraries ...........................................................................199
3.10.7 Optimizations for Size ...........................................................................199
3.10.7.1 Space/Performance Trade Off ...................................................199
4.0 Network Processor Engines (NPE) .........................................................................202
5.0 Internal Bus...........................................................................................................204
5.1 Internal Bus Arbiters........................................................................................204
5.1.1 Priority Mechanism................................................................................205
5.2 Memory Map...................................................................................................205
6.0 PCI Controller........................................................................................................208
6.1 PCI Controller Configured as Host......................................................................213
6.1.1 Example: Generating a PCI Configuration Write and Read .......................... 216
6.2 PCI Controller Configured as Option...................................................................218