Intel IXC1100, IXP42X

Intel® IXP42X product line and IXC1100 control plane processors—Ethernet MAC A

Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor

DM September 2006

422 Order Number: 252480-006US

Transmit Control Register 1 can be accessed directly. Intel, however, recommends that

the Transmit Control Register 1 values be manipulated through Intel supplied APIs.

Failure to use the Intel-supplied APIs will result in unpredictable results.

The Transmit Engine also can be configured to append additional bytes to frames that

are smaller than the 64-byte frame minimum. When the transmit engine observes that

the length field is smaller than 64 bytes — and bit 3 of the Transmit Control Register 1

(TXCTRL1) is set to logic 1 — the transmit engine will append additional bytes to equal

the 64-byte minimum size. A CRC value will be calculated over the appended bytes.

The appended bytes will be all zeros.

Transmit Control Register 1 can be accessed directly, but Intel recommends that the

Transmit Control Register 1 values be manipulated through Intel-supplied APIs. Failure

to use the Intel-supplied APIs will result in unpredictable results.

The IXP42X product line and IXC1100 control plane processors also provide the

capability to enable or disable transmit retries. When bit 2 of the Transmit Control

attempt to retry sending the packet up to the maximum number of transmit retries

specified in bits (3:0) of Transmit Control Register 2 (TXCTRL2). A maximum of 16

retries can be attempted.

Note: Setting bit 1 of the Transmit Control Register 1 (TXCTRL1) to logic 1 configures a device

in half-duplex mode of operation. Setting the bit to logic 0 configures the device to full-

duplex mode.

If a packet is being transmitted and a collision is detected prior to 64 bytes of the

packet (minimum packet size) are transmitted, the transmit engine will rewind the

transmit FIFO pointer to the beginning of the frame that is being transmitted and

attempt to send the frame after a calculated back-off time, based upon the Slot Time

(SLOTTIME) Register.

If a packet is being transmitted and a collision is detected after 64 bytes of a packet

(minimum packet size) are transmitted, the transmit engine will forward the transmit

FIFO pointer to the beginning of the next packet that is to be transmitted and discard

the current packet that is being transmitted.

In a properly configured network, a collision should not occur after the first 64 bytes of

a packet is sent. The back-off time algorithm adheres to the IEEE 802.3 specifications

“truncated binary exponential algorithm.”

If the MII interface is configured in half-duplex mode of operation, the transmit

interface must listen to the activity on the line for a defined wait period called a

transmit deferral period. If there is any activity — transmit or receive — on the

medium, the transmit interface will defer the transmission of the packet that the

transmit engine has been requested to send.

When the transmit engine detects that the medium has gone silent, the transmit

engine will continue to defer for a period of time equal to the inter-frame spacing. The

deferral period will be assigned by the transmit deferral parameters. The transmit

deferral time can be specified as a one-part or an optional two-part deferral by

manipulating bit 5 of Transmit Control Register 1 (TXCTRL1).

Setting bits 5 of the Transmit Control Register 1 (TXCTRL1) to logic 1 enables the

optional, two-part transmit deferral. Setting bits 5 of the Transmit Control Register 1

(TXCTRL1) to logic 0 enables the one-part transmit deferral.

If the transmit engine has a frame ready to transmit and one-part transmit deferral is

selected, the transmit engine will wait for the medium to go silent and then wait for the

time period specified in the Transmit Deferral Register (TXDEFPARS). The deferral