Intel® IXP42X product line and IXC1100 control plane processors—PCI Controller
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
226 Order Number: 252480-006US
Target Interface is used to accept transaction request from other AHB Masters. The
AHB Master Interface is used to initiate transaction requests to other AHB Targets. The
two DMA channels as well as the PCI Target Interface use the AHB Master Interface.
The AHB Target Interface can accept 8-bit (1 Byte) transactions, 16-bit transactions,
and 32-bit transactions. Due to the South AHB not using byte enables, all 16-bit
transactions to the PCI Controller AHB Target Interface must be implemented as
consecutive-byte addresses. Inability to do this will result in multiple byte wide
transactions.
The AHB Master interface will initiate 8-bit (1 Byte) transactions and 32-bit (word)
transactions only. The DMA engines will initiate only 32-bit transactions. PCI Target
Interface initiated transactions will be 32-bit transactions. Sub 32-bit transactions —
initiated by the PCI Target Interface — will be implemented as multiple 8-bit
transactions initiated by the PCI Controller AHB Master on the AHB. For information on
prioritization of the three functional blocks that use the PCI Controller AHB Master
Interface, see “PCI Controller Functioning as Bus Initiator” on page 226.
6.6 PCI Controller Functioning as Bus Initiator
The IXP42X product line and IXC1100 control plane processors can be used to initiate
PCI transactions in one of three ways:
• Using the Non-Pre-fetch Registers — as described in section “PCI Controller
Configured as Host” on page 213
The Non-Pre-fetch Registers allow various single 32-bit word PCI Cycles to be
produced. The Non-Pre-fetch Registers can be used to initiate Type 0 Configuration
Cycles, Type 1 Configuration Cycles, Memory Cycles, I/O Cycles, and Special
Cycles.
• Writing to the PCI Memory Cycle Address Space located between AHB address
0x48000000 and 0x4BFFFFFF as described in section “Initializing PCI Controller
Configuration and Status Registers for Data Transactions” on page219
• Using the PCI Controller DMA channels — as described in “PCI Controller DMA
Controller” on page 234
The remainder of the section shows example of each cycle type that may be initiated.
The details in this section are provided to understand some functional aspects of the
PCI Controller on the IXP42X product line and IXC1100 control plane processors. For
complete details please refer to the PCI Local Bus Specification, Rev.2.2.

6.6.1 PCI Byte Enables

I/O reads and memory-cycle writes drive individual byte enables. However, it is
important to note that the PCI controller drives all byte enables low (asserted) during a
memory cycle read of non-prefetch memory.
If an ext ernal PCI device ha s non-pre fetch mem ory and re quires ei ther a 16- bit or 8-b it
read, there is a possibility that the device will not respond correctly to IXP42X product
line and IXC1100 control plane processors memory reads. This is because the IXP42X
product line and IXC1100 control plane processors always perform a 32-bit read to the
non-prefetch memory region specified in register PCI_NP_AD.
The 8-bit or 16-bit external device should respond with a “target abort,” as per the PCI
2.2 specification, if a 32-bit read is performed to its non-prefetch memory and it
requires a 16-bit or 8-bit read.