Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 5
—Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
3.6.11.2 SELDCSR JTAG Register...........................................................103
3.6.11.3 DBGTX JTAG Command........................................................... 105
3.6.11.4 DBGTX JTAG Register..............................................................105
3.6.11.5 DBGRX JTAG Command...........................................................106
3.6.11.6 DBGRX JTAG Register..............................................................106
3.6.11.7 Debug JTAG Data Register Reset Values.....................................109
3.6.12 Trace Buffer ........................................................................................109
3.6.12.1 Trace Buffer CP Registers.........................................................109
3.6.13 Trace Buffer Entries..............................................................................111
3.6.13.1 Message Byte.........................................................................111
3.6.13.2 Trace Buffer Usage..................................................................114
3.6.14 Downloading Code in ICache..................................................................116
3.6.14.1 LDIC JTAG Command.............................................................. 116
3.6.14.2 LDIC JTAG Data Register .........................................................117
3.6.14.3 LDIC Cache Functions..............................................................118
3.6.14.4 Loading IC During Reset.......................................................... 119
3.6.14.5 Dynamically Loading IC After Reset........................................... 123
3.6.14.6 Mini-Instruction Cache Overview............................................... 126
3.6.15 Halt Mode Software Protocol ..................................................................126
3.6.15.1 Starting a Debug Session.........................................................126
3.6.15.2 Implementing a Debug Handler................................................ 128
3.6.15.3 Ending a Debug Session ..........................................................131
3.6.16 Software Debug Notes and Errata........................................................... 132
3.7 Performance Monitoring................................................................................... 133
3.7.1 Overview ............................................................................................133
3.7.2 Register Description..............................................................................134
3.7.2.1 Clock Counter (CCNT)............................................................. 134
3.7.2.2 Performance Count Registers....................................................134
3.7.2.3 Performance Monitor Control Register........................................135
3.7.2.4 Interrupt Enable Register.........................................................136
3.7.2.5 Overflow Flag Status Register...................................................136
3.7.2.6 Event Select Register..............................................................137
3.7.3 Managing the Performance Monitor.........................................................138
3.7.4 Performance Monitoring Events.............................................................. 139
3.7.4.1 Instruction Cache Efficiency Mode............................................. 140
3.7.4.2 Data Cache Efficiency Mode......................................................140
3.7.4.3 Instruction Fetch Latency Mode................................................ 140
3.7.4.4 Data/Bus Request Buffer Full Mode............................................141
3.7.4.5 Stall/Write-Back Statistics........................................................141
3.7.4.6 Instruction TLB Efficiency Mode . ...............................................142
3.7.4.7 Data TLB Efficiency Mode.........................................................142
3.7.5 Multiple Performance Monitoring Run Statistics.........................................142
3.7.6 Examples............................................................................................142
3.8 Programming Model.........................................................................................144
3.8.1 ARM* Architecture Compatibility............................................................. 144
3.8.2 ARM* Architecture Implementation Options..............................................144
3.8.2.1 Big Endian versus Little Endian.................................................144
3.8.2.2 26-Bit Architecture..................................................................145
3.8.2.3 Thumb..................................................................................145
3.8.2.4 ARM* DSP-Enhanced Instruction Set..........................................145
3.8.2.5 Base Register Update..............................................................145
3.8.3 Extensions to ARM* Architecture.............................................................146
3.8.3.1 DSP Coprocessor 0 (CP0).........................................................146
3.8.3.2 New Page Attributes................................................................152
3.8.3.3 Additions to CP15 Functionality.................................................153
3.8.3.4 Event Architecture..................................................................154
3.9 Performance Considerations..............................................................................159