Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 99
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors
3.6.8.1 RX Register Ready Bit (RR)
The debugger and debug handler use the RR bit to synchronize accesses to RX.
Normally, the debugger and debug handler use a handshaking scheme that requires
both sides to poll the RR bit. To support higher download performance for large
amounts of data, a high-speed download handshaking scheme can be used in which
only the debug handler polls the RR bit before accessing the RX register, while the
debugger continuously downloads data.
Tabl e 39 shows the normal handshaking used to access the RX register.
When data is being downloaded by the debugger, part of the normal handshaking can
be bypassed to allow the download rate to be increased. Tabl e 40 shows the
handshaking used when the debugger is doing a high-speed download. Note that
before the high-speed download can start, both the debugger and debug handler must
be synchronized, such that the debug handler is executing a routine that supports the
high-speed download.
Although it is similar to the normal handshaking, the debugger polling of RR is
bypassed with the assumption that the debug handler can read the previous data from
RX before the debugger can scan in the new data.
Table 39. Normal RX Handshaking
Debugger Actions
• Debugger wants to send data to debug handler.
• Before writing new data to the RX register, the debugger polls RR through JTAG until the bit is cleared.
• After the debugger reads a ‘0’ from the RR bit, it scans data into JTAG to write to the RX register and sets
the valid bit. The write to the RX register automatically sets the RR bit.
Debug Handler Actions
• Debug handler is expecting data from the debugger.
• The debug handler polls the RR bit until it is set, indicating data in the RX register is valid.
• Once the RR bit is set, the debug handler reads the new data from the RX register. The read operation
automatically clears the RR bit.
Table 40. High-Speed Download Handshaking States
Debugger Actions
• Debugger wants to transfer code into IXP42X product line and IXC1100 control plane processors’ system
memory.
• Prior to starting download, the debugger must polls RR bit until it is clear. Once the RR bit is clear,
indicating the debug handler is ready, the debugger starts the download.
• The debugger scans data into JTAG to write to the RX register with the download bit and the valid bit set.
Following the write to RX, the RR bit and D bit are automatically set in TXRXCTRL.
• Without polling of RR to see whether the debug handler has read the data just scanned in, the debugger
continues scanning in new data into JTAG for RX, with the download bit and the valid bit set.
• An overflow condition occurs if the debug handler does not read the previous data before the debugger
completes scanning in the new data, (See “Overflow Flag (OV)” on page100 for more details on the
overflow condition).
• After completing the download, the debugger clears the D bit allowing the debug handler to exit the
download loop.
Debug Handler Actions
• Debug is handler in a routine waiting to write data out to memory. The routine loops based on the D bit in
TXRXCTRL.
• The debug handler polls the RR bit until it is set. It then reads the Rx register, and writes it out to memory.
The handler loops, repeating these operations until the debugger clears the D bit.