Intel IXC1100, IXP42X (TXRXCTRL)

Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor

Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor

DM September 2006

98 Order Number: 252480-006US

On a data breakpoint, the processor generates a debug exception and re-directs

execution to the debug handler before the next instruction executes. The processor

reports the data breakpoint by setting the DCSR.MOE to 0b010. The link register of a

data breakpoint is always PC (of the next instruction to execute) + 4, regardless of

whether the processor is configured for monitor mode or halt mode.

3.6.7 Software Breakpoints

Mnemonics: BKPT (See ARM* Architecture Reference Manual, ARMv5T)

Operation: If DCSR[31] = 0, BKPT is a nop;

If DCSR[31] =1, BKPT causes a debug exception

The processor handles the software breakpoint as described in “Debug Exceptions” on

page 92.

3.6.8 Transmit/Receive Control Register

(TXRXCTRL)

Communications between the debug handler and debugger are controlled through

handshaking bits that ensures the debugger and debug handler make synchronized

accesses to TX and RX. The debugger side of the handshaking is accessed through the

DBGTX (“DBGTX JTAG Register” on page105) and DBGRX (“DBGRX JTAG Register” on

page 106) JTAG Data Registers, depending on the direction of the data transfer.The

debug handler uses separate handshaking bits in TXRXCTRL register for accessing TX

and RX.

The TXRXCTRL register also contains two other bits that support high-speed download.

One bit indicates an overflow condition that occurs when the debugger attempts to

write the RX register before the debug handler has read the previous data written to

RX. The other bit is used by the debug handler as a branch flag during high-speed

download.

All of the bits in the TXRXCTRL register are placed such that they can be read directly

into the CC flags in the CPSR with an MRC (with Rd = PC). The subsequent instruction

can then conditionally execute based on the updated CC value

Table 38. TX RX Control Register (TXRXCTRL)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210

VDT

reset value: 0x00000000

Bits Access Description

31 SW Read-only / Write-ignored

JTAG Write-only

RX Register Ready

30 SW Read / Write OV

RX overflow sticky flag

29 SW Read-only/ Write-ignored

JTAG Write-only

High-speed download flag

28 SW Read-only/ Write-ignored

JTAG Write-only

TX Register Ready

27:0 Read-as-Zero / Write-ignored Reserved