Intel IXC1100, IXP42X 6.11 PCI Controller Endian Control

Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 241
PCI Controller—Intel® IXP42X product line and IXC1100 control plane processors
• A Doorbell is “pushed” by an external PCI device
The PCI Interrupt Status Register (PCI_ISR) indicates the source(s) of the PCI
Controller Interrupt signal (PCC_INT). The PCI Controller Interrupt Enable
(PCC_INTEN) Register provides an enable for each of the sources located in the PCI
Interrupt Status Register (PCI_ISR).
When a bit is set in PCI Interrupt Status Register (PCI_ISR) and the corresponding bit
is enabled in the PCI Interrupt Enable (PCI_INTEN) register, then the PCI Controller
Interrupt (PCC_INT) signal will be asserted to the Interrupt Controller and then the
Intel XScale processor. The interrupt remains asserted until either the source of the
interrupt in the PCI Interrupt Status (PCI_ISR) register is cleared or the enable in the
PCI Interrupt Enable (PCI_INEN) Register is cleared.
Clearing an interrupt source may involve clearing bits in other Configuration and Status
registers.
The PCI_AHBDOORBELL register is used to generate the doorbell interrupt to an AHB
agent. This register is read/write-1-to-set from the PCI bus, and read/write-1-to-clear
from the AHB bus. All bits are ORed together to generate the interrupt. The sequence
is:
1. An external PCI agent writes a pattern of ones to the PCI_AHBDOORBELL register,
setting the corresponding bits in the register and asserting the interrupt to the AHB
agent.
2. The AHB agent reads the bit pattern in the doorbell register and writes the same
pattern back to clear the bits and de-assert the interrupt.
6.11 PCI Controller Endian Control
The PCI Local Bus Specification, Rev.2.2 defines the byte-addressing convention on the
PCI Bus as little endian. Since the byte-addressing convention on the PCI bus is defined
as little endian and the convention used on the IXP42X product line and IXC1100
control plane processors’ AHB bus is defined as big-endian, the data passing from the
PCI bus and the South AHB may be translated from one endianness to the other
endianness.
The endian translation can be done by software implemented on the Intel XScale
processor. However, several endianness hardware assist functions have been added to
the PCI Controller to help remove the endian-swapping burden from the Intel XScale
processor, when 32-bit word transactions are occurring on the PCI bus.
There is a hardware-assist function that provides a 32-bit-word-wide, byte-lane
reversal process when the IXP42X product line and IXC1100 control plane processors is
being used as a PCI target, when the IXP42X product line and IXC1100 control plane
processors are initiating PCI Bus transactions using the PCI Memory Cycle Address
Space (AHB address 0x48000000 to 0x4BFFFFFF), and the DMA channels are being
used as described previously.
There are three bits of the PCI Controller Control and Status Register (PCI_CSR) that
control the steering of addresses between the South AHB and PCI Bus when the IXP42X
product line and IXC1100 control plane processors are being used as a PCI target and
when the IXP42X product line and IXC1100 control plane processors are initiating PCI
Bus transactions using the PCI Memory Cycle Address Space (AHB address
0x48000000 to 0x4BFFFFFF). These three bits are:
• Bit 4 (AHB Big-endian Addressing Mode)
• Bit 3 (PCI Target Transfer Byte Swap)
• Bit 2 (AHB Memory Mapped Byte Swap).