Intel IXC1100, IXP42X manual - page 8

Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor—
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
8Order Number: 252480-006US
6.14.2.11DMA Control Register...............................................................265
6.14.2.12AHB Memory Base Address Register...........................................266
6.14.2.13AHB I/O Base Address Register.................................................266
6.14.2.14PCI Memory Base Address Register............................................267
6.14.2.15AHB Doorbell Register..............................................................267
6.14.2.16PCI Doorbell Register...............................................................268
6.14.2.17AHB to PCI DMA AHB Address Register 0....................................268
6.14.2.18AHB to PCI DMA PCI Address Register 0.....................................269
6.14.2.19AHB to PCI DMA Length Register 0............................................269
6.14.2.20AHB to PCI DMA AHB Address Register 1....................................270
6.14.2.21AHB to PCI DMA PCI Address Register 1.....................................270
6.14.2.22AHB to PCI DMA Length Register 1............................................270
6.14.2.23PCI to AHB DMA AHB Address Register 0....................................271
6.14.2.24PCI to AHB DMA PCI Address Register 0.....................................271
6.14.2.25PCI to AHB DMA Length Register 0............................................272
6.14.2.26PCI to AHB DMA AHB Address Register 1....................................272
6.14.2.27PCI to AHB DMA PCI Address Register 1.....................................273
6.14.2.28PCI to AHB DMA Length Register 1............................................273
7.0 SDRAM Controller ..................................................................................................276
7.1 SDRAM Memory Space.....................................................................................279
7.2 Initializing the SDRAM Controller .......................................................................279
7.2.1 Initializing the SDRAM...........................................................................283
7.3 SDRAM Memory Accesses.................................................................................285
7.3.1 Read Transfer ......................................................................................285
7.3.1.1 Read Cycle Timing (CAS Latency of Two Cycles)..........................285
7.3.1.2 Read Burst Transfer (Interleaved AHB Reads).............................286
7.3.2 Write Transfer......................................................................................286
7.3.2.1 Write Transfer.........................................................................286
7.4 Register Description.........................................................................................287
7.4.1 Configuration Register...........................................................................287
7.4.2 Refresh Register...................................................................................288
7.4.3 Instruction Register ..............................................................................288
8.0 Expansion Bus Controller.......................................................................................292
8.1 Expansion Bus Address Space ...........................................................................293
8.2 Chip Select Address Allocation...........................................................................294
8.3 Address and Data Byte Steering ........................................................................295
8.4 Expansion Bus Connections...............................................................................297
8.5 Expansion Bus Interface Configuration................................................................298
8.6 Using I/O Wait ................................................................................................301
8.7 Special Design Knowledge for Using HPI mode.....................................................303
8.8 Expansion Bus Interface Access Timing Diagrams.................................................305
8.8.1 Intel® Multiplexed-Mode Write Access.....................................................305
8.8.2 Intel® Multiplexed-Mode Read Access......................................................306
8.8.3 Intel® Simplex-Mode Write Access..........................................................307
8.8.4 Intel® Simplex-Mode Read Access...........................................................308
8.8.5 Motorola* Multiplexed-Mode Write Access................................................309
8.8.6 Motorola* Multiplexed-Mode Read Access.................................................310
8.8.7 Motorola* Simplex-Mode Write Access.....................................................311
8.8.8 Motorola* Simplex-Mode Read Access.....................................................312
8.8.9 TI* HPI-8 Write Access..........................................................................313
8.8.10 TI* HPI-8 Read Access..........................................................................314
8.8.11 TI* HPI-16, Multiplexed-Mode Write Access..............................................315
8.8.12 TI* HPI-16, Multiplexed-Mode Read Access..............................................316
8.8.13 TI* HPI-16 Simplex-Mode Write Access ...................................................317
8.8.14 TI* HPI-16 Simplex-Mode Read Access....................................................318