Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 541
UTOPIA Level-2—Intel® IXP42X product line and IXC1100 control plane processors
To allow the most flexibility, a logical address to physical address table is provided. The
look-up table makes it possible for the five addresses — that were called out, above —
not to be in sequential order. For example, the following logical to physical address map
could be used for the above example of five physical interfaces.
• Logical Address 0 => Physical Address 3 => UTP_TX_ADDR lines = 00011
• Logical Address 1 => Physical Address 5 => UTP_TX_ADDR lines = 00101
• Logical Address 2 => Physical Address 7 => UTP_TX_ADDR lines = 00111
• Logical Address 3 => Physical Address 9 => UTP_TX_ADDR lines = 01001
• Logical Address 4 => Physical Address 22 => UTP_TX_ADDR lines = 10110
Once the physical address is driven to all physical interfaces, using the UTP_TX_ADDR
signals, the physical interface is ready to accept a cell. The physical interface is
configured to the address signals that match the values contained on the
UTP_TX_ADDR signals and responds to the UTOPIA Level-2 interface on the IXP42X
product line and IXC1100 control plane processors by driving their UTP_OP_FCI (a.k.a
TX_FULL_N/TX_CLAV) signal to inform the UTOPIA Level-2 Interface that the physical
interface is ready to receive a cell.
The Transmit Port Status (TXPORTSTAT) register — contained within the Transmit
Module — stores the polling result for each of the physical interfaces. The Network
Processor Engine core uses the values stored in the Transmit Port Status
(TXPORTSTAT) Register to select a physical interface that is ready to complete a
transfer and loads the Transmit FIFO.
The Transmit FIFO informs the Transmit Module that a cell is ready to be transmitted to
a specific physical interface. The Transmit Module will then remove the cell information
from the Transmit FIFO and begin transmitting the data to the specified physical
interface. It is important to note that the NPE code will send to the Transmit Module the
logical port address of the physical interface to be selected along with the cell data.
This feature allows the NPE to have full control over transmitted data based upon the
polling status returned from the hardware.
While transmitting the data, an optional head-error correction (HEC) value can be
calculated from the header and inserted into the data stream. The HEC generation unit
takes the header data and uses the data with an internal, 8-bit HEC cyclical redundancy
check (CRC) residue register to produce the value for the next HEC CRC residue. The
HEC is generated new for every cell transmitted and has no dependencies on previous
cells transmitted.
The HEC residue may be inserted directly into the data stream being transmitted over
the UTOPIA Level-2 interface or, optionally, the HEC residue may be exclusive-ORed
with hexadecimal 0x55 — to generate a COSET value, before being inserted into the
data stream.
The HEC value is available one clock period after the last byte of the header information
is transmitted. Therefore, a complete stream of cell data (H0, H1, H2, H3, HEC, D0, D1,
…) can be transmitted in successive clock cycles without interruption to the data
stream.
When the Transmit HEC (TxHEC) configuration bit is enabled, the UTOPIA transmit
interface will always insert an extra byte (valid HEC) into the cell being transmitted. In
normal operation (TxHEC is enabled), the UTOPIA Level-2 Coprocessor Transmit Module
will expect 52 bytes from the Transmit FIFO and the Transmit Module will insert a valid
HEC field into the data stream.
Figure 98 shows the transmission of a cell in multiple-PHY (MPHY) mode. The following
assumptions are made for the figure: