Intel IXC1100, IXP42X 3.10.5.6 Scheduling the MIA and MIAPH Instructions, 3.10.5.7 Scheduling MRS and MSR Instructions

Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
198 Order Number: 252480-006US
The MAR (MCRR) instruction has an issue latency, a result latency, and a resource
latency of two cycles. Due to the two-cycle issue latency, the pipeline would always stall
for one cycle following a MAR instruction. The use of the MAR instruction should,
therefore, be used only where absolutely necessary.
3.10.5.6 Scheduling the MIA and MIAPH Instructions
The MIA instruction has an issue latency of one cycle. The result and resource latency
can vary from one to three cycles depending on the values in the source register.
Consider the following code sample:
The second MIA instruction above can stall from zero to two cycles depending on the
values in the registers r2 and r3 due to the one-to-three-cycle resource latency.
Similarly, consider the following code sample:
The MRA instruction above can stall from zero to two cycles depending on the values in
the registers r2 and r3 due to the one-to-three-cycle result latency.
The MIAPH instruction has an issue latency of one cycle, result latency of two cycles
and a resource latency of two cycles.
Consider the code sample shown below:
The second MIAPH instruction would stall for one-cycle due to a two-cycle resource
latency. The MRA instruction would stall for one-cycle due to a two-cycle result latency.
These stalls can be avoided by rearranging the code as follows:
3.10.5.7 Scheduling MRS and MSR Instructions
The MRS instruction has an issue latency of one cycle and a result latency of two
cycles. The MSR instruction has an issue latency of 2 cycles (6 if updating the mode
bits) and a result latency of one cycle.
mra r6, r7, acc0
add r2, r2, #1
mov r0, r6
mov r1, r7
mia acc0, r2, r3
mia acc0, r4, r5
mia acc0, r2, r3
mra r4, r5, acc0
add r1, r2, r3
miaph acc0, r3, r4
miaph acc0, r5, r6
mra r6, r7, acc0
sub r8, r3, r4
miaph acc0, r3, r4
add r1, r2, r3
miaph acc0, r5, r6
sub r8, r3, r4
mra r6, r7, acc0