Intel IXC1100, IXP42X 11.0 Internal Bus Performance Monitoring Unit (IBPMU)

Intel® IXP42X product line and IXC1100 control plane processors—Internal Bus Performance

Monitoring Unit (IBPMU)

Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor

DM September 2006

372 Order Number: 252480-006US

11.0 Internal Bus Performance Monitoring Unit (IBPMU)

The Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane

Processor’ Internal Bus Performance Monitoring Unit (IBPMU) may be used to gather

statistics about transactions occurring on North AHB, South AHB, and the SDRAM

Controller. These statistics can be used to optimize the software running on the Intel

XScale® Processor which, in turn, will improve overall system performance.

There are two types of events that can be measured: occurrence and duration.

An occurrence event is an action that occurs periodically and is measured by counting

the number of times that the event occurred. An example of an occurrence event is

counting the number of times the Intel XScale processor requests the AHB bus.

A duration event is an action that measures the amount of time it takes to complete a

requested action. For example, a duration event could be keeping track of the amount

of time the Intel XScale® Processor spends requesting the South AHB before it is

granted mastership to the South AHB.

The occurrence event and the duration event, used in the examples above, could be

used to determine the average amount of delay the Intel XScale processor is

experiencing in acquiring the South AHB.

The IBPMU statistics are gathered in seven 27-bit, programmable event counters

(PEC). The counter size was chosen to allow the measurement of a duration event to be

approximately 1 second for 133-MHz accesses. The 133-MHz accesses originate from

the speed of the North AHB, South AHB, and the SDRAM Controller.

Therefore, when a duration event is monitored and the programmable event counter

rolls over, an interrupt is generated. The programmable event counter will have

measured 1 second in time. Whenever a programmable event counter rolls over, the

counter will set a bit in a local interrupt status register and start counting from zero. All

the bits from the status register will be combined to send a single interrupt signal that

is sent to the Interrupt Controller.

The seven 27-bit programmable event counters can monitor the events — shown in

Tabl e 140 and Table 141 — by setting the values in the 32-bit Event Select Register

(ESR). The Event Select Register is broken up into seven 3-bit registers that indicate

the event type to monitor, occurrence or duration, and the exact event.

The three bits associated with Programmable Event Counter 1 are located in bits 20

through 22 of the Event Select Register. The three bits associated with Programmable

Event Counter 7 are located in bits 2 through 4 of the Event Select Register. All other

programmable event counter configurations are in 3-bit increments, going down from

bit 19 down to bit 2. (For example, PEC2 is configured by bits 19 through 17 of the

event select register and PEC3 is configured by bits 16 through 14 of the event select