Intel IXC1100, IXP42X 3.8 Programming Model

Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
144 Order Number: 252480-006US
In the contrived example above, the instruction cache had a miss-rate of 5% and CPI
was 2.4.
3.8 Programming Model
This section describes the programming model of the IXP42X product line and IXC1100
control plane processors, namely the implementation options and extensions to the
ARM Version 5TE architecture.
3.8.1 ARM* Architecture Compatibility
The IXP42X product line and IXC1100 control plane processors implement the integer
instruction set architecture specified in ARM V5TE. T refers to the thumb instruction set
and E refers to the DSP-Enhanced instruction set.
ARM V5TE introduces a few more architecture features over ARM V4, specifically the
addition of tiny pages (1 Kbyte), a new instruction that counts the leading zeroes (CLZ)
in a data value, enhanced ARM-Thumb transfer instructions and a modification of the
system control coprocessor, CP15.
3.8.2 ARM* Architecture Implementation Options
3.8.2.1 Big Endian versus Little Endian
The IXP42X product line and IXC1100 control plane processors can operate in big or
little endian mode. The B-bit of the Control Register, coprocessor15, register 1, bit 7
(see Section 3.5.1.2) contained within the IXP42X product line and IXC1100 control
plane processors selects the endianess mode of the Intel XScale processor.
Note: This bit takes effect even if the MMU is disabled.
If you choose little endian then you have further options that control whether address
and/or data coherency modes. Refer P-Attribute bit in the MMU (see Section 3.1.1.1,
“Page (P) Attribute Bit” on page 45) and Expansion Bus Configuration Register 1, Bit 8,
BYTE_SWAP_EN (Table126, “Expansion Bus Configuration Register 1-Bit Definition” on
page 325).
Note: The NPEs on the IXP42X product line and IXC1100 control plane processors are Big-
Endian only; so if you change the endianess of the Intel XScale processor to little
endian for your operating system, then this has an impact on how the NPEs and Intel
XScale processor exchange data. The Intel® IXP400 Software Release handles this.
Example 16. Computing the Results
; Assume CCNT overflowed
CCNT = 0x0000,0020 ;Overflowed and continued counting
Number of instructions executed = PMN0 = 0x6AAA,AAAA
Number of instruction cache miss requests = PMN1 = 0x0555,5555
Instruction Cache miss-rate = 100 * PMN1/PMN0 = 5%
CPI = (CCNT + 2^32)/Number of instructions executed = 2.4 cycles/instruction