Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 11
—Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
14.4.9 Timer Status........................................................................................415
15.0 Ethernet MAC A.....................................................................................................416
15.1 Ethernet Coprocessor.......................................................................................417
15.1.1 Ethernet Coprocessor APB Interface........................................................418
15.1.2 Ethernet Coprocessor NPE Interface........................................................418
15.1.3 Ethernet Coprocessor MDIO Interface .....................................................418
15.1.4 Transmitting Ethernet Frames with MII Interfaces.....................................420
15.1.5 Receiving Ethernet Frames with MII Interfaces......................................... 423
15.1.6 General Ethernet Coprocessor Configuration ............................................425
15.2 Register Descriptions.......................................................................................427
15.2.1 Transmit Control 1 ...............................................................................428
15.2.2 Transmit Control 2 ...............................................................................429
15.2.3 Receive Control 1.................................................................................429
15.2.4 Receive Control 2.................................................................................430
15.2.5 Random Seed......................................................................................430
15.2.6 Threshold For Partially Empty.................................................................431
15.2.7 Threshold For Partially Full.....................................................................431
15.2.8 Buffer Size For Transmit........................................................................431
15.2.9 Transmit Deferral Parameters................................................................ 432
15.2.10Receive Deferral Parameters.................................................................. 432
15.2.11Transmit Two Part Deferral Parameters 1 ................................................ 433
15.2.12Transmit Two Part Deferral Parameters 2 ................................................ 433
15.2.13Slot Time ............................................................................................433
15.2.14MDIO Commands Registers ...................................................................434
15.2.15MDIO Command 1................................................................................434
15.2.16MDIO Command 2................................................................................434
15.2.17MDIO Command 3................................................................................435
15.2.18MDIO Command 4................................................................................435
15.2.19MDIO Status Registers.......................................................................... 435
15.2.20MDIO Status 1..................................................................................... 436
15.2.21MDIO Status 2..................................................................................... 436
15.2.22MDIO Status 3..................................................................................... 436
15.2.23MDIO Status 4..................................................................................... 436
15.2.24Address Mask Registers.........................................................................437
15.2.25Address Mask 1....................................................................................437
15.2.26Address Mask 2....................................................................................438
15.2.27Address Mask 3....................................................................................438
15.2.28Address Mask 4....................................................................................438
15.2.29Address Mask 5....................................................................................438
15.2.30Address Mask 6....................................................................................439
15.2.31Address Registers.................................................................................439
15.2.32Address 1............................................................................................440
15.2.33Address 2............................................................................................440
15.2.34Address 3............................................................................................440
15.2.35Address 4............................................................................................440
15.2.36Address 5............................................................................................441
15.2.37Address 6............................................................................................441
15.2.38Threshold for Internal Clock...................................................................442
15.2.39Unicast Address Registers......................................................................442
15.2.40Unicast Address 1.................................................................................443
15.2.41Unicast Address 2.................................................................................443
15.2.42Unicast Address 3.................................................................................443
15.2.43Unicast Address 4.................................................................................443
15.2.44Unicast Address 5.................................................................................444