Intel IXC1100, IXP42X - page 46

Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
46 Order Number: 252480-006US
3.1.1.2.2 Details on Data Cache and Write Buffer Behavior
If the MMU is disabled, all data accesses will be non-cacheable and non-bufferable. This
is the same behavior as when the MMU is enabled and a data access uses a descriptor
with X, C, and B all set to 0.
The X, C, and B bits determine when the processor should place new data into the Data
Cache. The cache places data into the cache in lines (also called blocks). Thus, the
basis for making a decision about placing new data into the cache is a called a “Line-
Allocation Policy.”
If the Line-Allocation Policy is read-allocate, all load operations that miss the cache,
request a 32-byte cache line from external memory and allocate it into either the data
cache or mini-data cache. (This statement assumes that the cache is enabled.) Store
operations that miss the cache will not cause a line to be allocated.
If read/write-allocate is in effect, load or store operations that miss the cache will
request a 32-byte cache line from external memory if the cache is enabled.
The other policy determined by the X, C, and B bits is the Write Policy. A write-through
policy instructs the data cache to keep external memory coherent by performing stores
to both external memory and the cache. A write-back policy only updates external
memory when a line in the cache is cleaned or needs to be replaced with a new line.
Generally, write-back provides higher performance because it generates less data
traffic to external memory. For more details on cache policies, see “Cacheability” on
page 63
3.1.1.2.3 Data Cache and Write Buffer
All of these descriptor bits affect the behavior of the Data Cache and the Write Buffer.
If the X bit for a descriptor is zero, the C and B bits operate as mandated by the ARM
architecture, refer to the ARM* Architecture Reference Manual. This behavior is
detailed in Tabl e 3.
If the X bit for a descriptor is one, the C and B bits’ meaning is extended, as detailed in
Tabl e 4.
Table 3. Data Cache and Buffer Behavior When X = 0
C B Cacheable Bufferable Write Policy Line Allocation
Policy Notes
0 0 N N - - Stall until complete*
01 N Y - -
1 0 Y Y Write Through Read Allocate
1 1 Y Y Write Back Read Al l ocate
Note: Normally, the processor will continue executing after a data access if no dependency on that access is
encountered. With this setting, the processor will stall execution until the data access completes. This
guarantees to software that the data access has taken effect by the time execution of the data access
instruction completes. External data aborts from such accesses will be imprecise (but see “Data
Aborts” on page156 for a method to shield code from this imprecision).