Intel IXC1100, IXP42X 3.2 Instruction Cache

Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
52 Order Number: 252480-006US
Only entries 0 through 30 can be locked in either TLB; entry 31can never be locked. If
the lock pointer is at entry 31, a lock operation will update the TLB entry with the
translation and ignore the lock. In this case, the round-robin pointer will stay at
entry 31.
3.2 Instruction Cache
The Intel XScale processor instruction cache enhances performance by reducing the
number of instruction fetches from external memory. The cache provides fast execution
of cached code. Code can also be locked down when guaranteed or fast access time is
required.
Figure 8 shows the cache organization and how the instruction address is used to
access the cache.
The instruction cache is available as a 32 K, 32-way set, associative cache. Each set is
1,024 bytes in size. Each set contains 32 ways. Each way of a set contains eight 32-bit
words and one valid bit, which is referred to as a line. The replacement policy is a
round-robin algorithm and the cache also supports the ability to lock code in at a line
granularity.
The instruction cache is virtually addressed and virtually tagged.
Note: The virtual address presented to the instruction cache may be remapped by the PID
register. For a description of the PID register, see “Register 13: Process ID” on page84.
3.2.1 Operation When Instruction Cache is Enabled
When the cache is enabled, it compares every instruction request address against the
addresses of instructions that it is currently holding. If the cache contains the
requested instruction, the access “hits” the cache, and the cache returns the requested
instruction. If the cache does not contain the requested instruction, the access “misses”
the cache. The cache requests an eight-word, also known as a line, fetch from external
memory that contains the requested instruction using the fetch policy described in
“Instruction-Cache ‘Miss’” on page 53. As the fetch returns instructions to the cache,
the instructions are placed in one of two fetch buffers and the requested instruction is
delivered to the instruction decoder.
Figure 7. Example of Locked Entries in TLB
entry 0
entry 1
entry 7
entry 8
entry 22
entry 23
entry 30
entry 31
Locked
Eight entries locked, 24 entries available for
round robin replacement