Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
54 Order Number: 252480-006US
• A fetch buffer is allocated
• The instruction cache sends a fetch request to the external bus. This request is for
a 32-byte line.
• Instructions words are returned back from the external bus, at a maximum rate of
1 word per core cycle. The instruction cache can have the eight words of data
return in any order, which allows the Intel XScale processor to send the requested
instruction first, thus reducing fetch latency. (This is referred to as critical word
first.)As each word returns, the corresponding valid bit is set for the word in the
fetch buffer.
• As soon as the fetch buffer receives the requested instruction, it forwards the
instruction to the instruction decoder for execution.
• When all words have returned, the fetched line will be written into the instruction
cache if it’s cacheable and if the instruction cache is enabled. The line chosen for
update in the cache is controlled by the round-robin replacement algorithm. This
update may evict a valid line at that location. For more information on enabling or
disabling instruction cache, refer to “Instruction-Cache Coherence” on page 55
1. Once the cache is updated, the eight valid bits of the fetch buffer are invalidated.
3.2.1.2 Instruction-Cache Line-Replacement Algorithm
The line replacement algorithm for the instruction cache is round-robin. Each set in the
instruction cache has a round-robin pointer that keeps track of the next line (in that
set) to replace. The next line to replace in a set is the one after the last line that was
written. For example, if the line for the last external instruction fetch was written into
way 5-set 2, the next line to replace for that set would be way 6. None of the other
round-robin pointers for the other sets are affected in this case.
After reset, way 31 is pointed to by the round-robin pointer for all the sets. Once a line
is written into way 31, the round-robin pointer points to the first available way of a set,
beginning with way0 if no lines have been locked into that particular set. Locking lines
into the instruction cache effectively reduces the available lines for cache updating. For
example, if the first three lines of a set were locked down, the round-robin pointer
would point to the line at way 3 after it rolled over from way 31. For more details on
cache locking, see “Instruction-Cache Coherence” on page 55.
The instruction cache is protected by parity to ensure data integrity. Each instruction
cache word has 1 parity bit. (The instruction cache tag is NOT parity protected.) When
a parity error is detected on an instruction cache access, a prefetch abort exception
occurs if the Intel XScale processor attempts to execute the instruction. Before
servicing the exception, hardware places a notification of the error in the Fault Status
Register (Coprocessor 15, register 5).
A software exception handler can recover from an instruction cache parity error. The
parity error can be accomplished by invalidating the instruction cache and the branch
target buffer and then returning to the instruction that caused the prefetch abort
exception. A simplified code example is shown in Example 4 on page 55. A more
complex handler might choose to invalidate the specific line that caused the exception
and then invalidate the BTB.