Intel® IXP42X product line and IXC1100 control plane processors—Ethernet MAC A
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
418 Order Number: 252480-006US
•MII Interface
• Management Data Interface
15.1.1 Ethernet Coprocessor APB Interface
The APB interface is used to allow the Intel XScale® Processor to communicate directly
to configuration and control registers utilized by the Media Access Controller. The
Ethernet coprocessor’s APB interface will be used to configure the Ethernet MAC,
monitor Ethernet status, and configure the physical devices connected via the MII
interfaces. The physical devices connected to the MII interface will be configured using
the shared Management Data Interface.
15.1.2 Ethernet Coprocessor NPE Interface
The NPE Coprocessor Interface is used to communicate between the Ethernet
coprocessor and the NPE core. The NPE coprocessor interface will be used to transfer
incoming and outgoing data traffic to and from the NPE core. The NPE core — along
with other coprocessor — will take the Ethernet data and perform data manipulation,
forward the data to the SDRAM, and update the Queue Manager.
15.1.3 Ethernet Coprocessor MDIO Interface
The Management Data Interface is a two-wire interface that resides in NPE B and
supports both MII Interfaces. The Management Data Interface consists of the
Management Data Input/Output (MDIO) signal and the Management Data Clock (MDC).
The Management Data Input/Output signal is a bi-directional signal that is used to
transfer control, configuration, and status information between the IXP42X product line
and IXC1100 control plane processors and any peripheral devices connected to the MII
interfaces.
The Ethernet Coprocessor is initiated twice to support two Ethernet PHYs outside the
device. However, only the MDC and MDIO of one of the coprocessors were brought out
and they are used to program both Ethernet PHYs.
The Management Data Clock can be configured as an input or an output, enabling the
IXP42X product line and IXC1100 control plane processors to source the Management
Data Clock or enable an external device to source the clock. The Management Date
Clock is used to clock the data sent on the Management Data Input/Output Signal.
Data transfers will be initiated over the MDIO using the MDIO Command Register
(MDIOC MD). Th e MDIO C ommand Regist er is br oken in to four 8-bit r egiste rs tha t make
up a full 32-bit command word.
If data is to be sent to the PHY over the MDIO interface, the Intel XScale processor will
write a value to each of the four command words in sequential order:
• MDIO Command 1 (MDIOCMD1) Register and MDIO Command 2 (MDIOCMD2)
Register will contain the 16 bits of data that the destination PHY will receive.
• MDIO Command 3 (MDIOCMD3) Register and MDIO Command 4 (MDIOCMD4)
Register will determine which PHY number is to be addressed, the internal register
of the addressed PHY, the direction of the access (read/write), and when to begin
the access.
There can be a limit of 32 physical ports and a limit of 32 registers per physical port
that may be addressed.
MDIOCMD3 makes up bits (23:16) of MDIOCMD and MDIOCMD4 make up bits (31:24):