Intel IXC1100, IXP42X 3.10.6 Optimizing C Libraries, 3.10.7 Optimizations for Size

Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 199
Intel XScale® Processor—Intel® IXP42X product line and IXC1100 control plane processors
Consider the code sample:
The ORR instruction above would incur a one cycle stall due to the two-cycle result
latency of the MRS instruction. In the code example above, the ADD instruction can be
moved before the ORR instruction to prevent this stall.
3.10.5.8 Scheduling CP15 Coprocessor Instructions
The MRC instruction has an issue latency of one cycle and a result latency of three
cycles. The MCR instruction has an issue latency of one cycle.
Consider the code sample:
The MOV instruction above would incur a two-cycle latency due to the three-cycle
result latency of the mrc instruction. The code shown above can be rearranged as
follows to avoid these stalls:
3.10.6 Optimizing C Libraries
Many of the standard C library routines can benefit greatly by being optimized for the
IXP42X product line and IXC1100 control plane processors architecture. The following
string and memory manipulation routines should be tuned to obtain the best
performance from the IXP42X product line and IXC1100 control plane processors’
architecture (instruction selection, cache usage and data prefetch):
strcat, strchr, strcmp, strcoll, strcpy, strcspn, strlen, strncat, strncmp, strpbrk, strrchr,
strspn, strstr, strtok, strxfrm, memchr, memcmp, memcpy, memmove, memset
3.10.7 Optimizations for Size
For applications such as cell phone software it is necessary to optimize the code for
improved performance while minimizing code size. Optimizing for smaller code size will,
in general, lower the performance of your application. This section contains techniques
for optimizing for code size using the IXP42X product line and IXC1100 control plane
processors instruction set.
3.10.7.1 Space/Performance Trade Off
Many optimizations mentioned in the previous sections improve the performance of
ARM code. However, using these instructions will result in increased code size. Use the
following optimizations to reduce the space requirements of the application code.
mrs r0, cpsr
orr r0, r0, #1
add r1, r2, r3
add r1, r2, r3
mrc p15, 0, r7, C1, C0, 0
mov r0, r7
add r1, r1, #1
mrc p15, 0, r7, C1, C0, 0
add r1, r2, r3
add r1, r1, #1
mov r0, r7