Intel IXC1100, IXP42X 5.2 Memory Map

Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor

September 2006 DM

Order Number: 252480-006US 205

Internal Bus—Intel® IXP42X product line and IXC1100 control plane processors

The arbiters also have the capability to handle split transfers. A split transfer is when:

• An AHB master request a read from a split capable AHB target

• The split capable AHB target issues a split transfer indication to the arbiter

• The arbiter allows other transactions to take place on the AHB while the AHB

master that issued the request that resulted in the split transfer waits on the read

data to be returned from the split capable AHB target

• The split capable AHB target completes the read transaction and notifies the arbiter

• The arbiter will grant the AHB master that requested the split transfer the bus in

the normal round robin progression

• The read data will be transferred from the split capable AHB target to the AHB

master that issued the request that resulted in the split transfer

All split capable AHB targets split a single AHB master read request at any given

instance. If the split capable AHB target receives another read request while servicing a

split transaction, the split capable AHB target will issue a retry. The only split capable

targets on the South AHB is the Expansion Bus. The only split capable target on the

North AHB is the AHB/AHB Bridge.

The arbiters send event information to the Internal Bus Performance Monitoring Unit

(IBPMU) so that the North AHB and South AHB bus performance can be observed. The

events that may be monitored are provided in section 3.11 Internal Bus Performance

Monitoring Unit (IBPMU).

The North AHB Arbiter is identical to the South AHB Arbiter in all respects except for

the bus masters and targets in which they are connected.

The arbiters allow the bus initiators access to the AHBs using a round-robin scheme.

Tabl e 95 illustrates a generic arbitration example for three AHB masters requesting the

AHB. The functionality of the independent arbiters is identical.

Each of the bus initiators (X, Y, and Z) is constantly requesting the bus. The bottom row

of Tabl e 95 lists the current bus initiator/winner of the initiators. For example, when all

three masters are requesting access, X will be the winner, and then Y and Z will be

requesting. Next, Y wins the AHB and X returns with a new request. So ZX are still valid

with Z being the oldest. Next, Z wins the bus, etc.

5.2 Memory Map

Tabl e 96 shows the memory map of peripherals connected to the AHB.

Table 95. Bus Arbitration Example: Three Requesting Masters

Initial +1+2+3+4+5+6+7+8+9

Requesting

Masters XYZ YZZXXYYZZXXYYZZXXY

Winning Bus

Initiator - XYZXYZXYZ