Intel IXC1100, IXP42X 6.4 Initializing the PCI Controller Configuration Registers

Intel® IXP42X product line and IXC1100 control plane processors—PCI Controller
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
222 Order Number: 252480-006US
• Bits 31:24 of the PCI Memory Base Address Register (PCI_PCIMEMBASE) register
correspond to the first 16-Mbyte window from South AHB address 0x48000000 to
0x48FFFFFF
• Bits 23:16 of the PCI Memory Base Address Register (PCI_PCIMEMBASE) register
correspond to the second 16-Mbyte window from South AHB address 0x49000000
to 0x49FFFFFF
• Bits 15:8 of the PCI Memory Base Address Register (PCI_PCIMEMBASE) register
correspond to the third 16-Mbyte window from South AHB address 0x4A000000 to
0x4AFFFFFF
• Bits 7:0 of the PCI Memory Base Address Register (PCI_PCIMEMBASE) register
correspond to the fourth 16-Mbyte window from South AHB address 0x4B000000
to 0x4BFFFFFF.
The PCI Memory Base Address Register (PCI_PCIMEMBASE) register is used to
determine the upper eight PCI address bits when the IXP42X product line and IXC1100
control plane processors access the memory spaces of external Targets on the PCI bus.
6.3.2 Example: PCI Memory Base Address Register and South-AHB
Translation
The following example discusses the operation of the PCI Memory Base Address
Register (PCI_PCIMEMBASE) and the South AHB translation.
1. Assume that PCI_PCIMEMBASE = 0xC3A24169.
2. The next example shows an access to the first 16-Mbyte window.
The South AHB address is for the access is 0x48123450. The address presented on
the PCI bus is 0xC3123450.
3. The next example shows an access to the second 16-Mbyte window.
The South AHB address is for the access is 0x49123450. The address presented on
the PCI bus is 0xA2123450.
4. The next example shows an access to the third 16-Mbyte window.
The South AHB address is for the access is 0x4A123450. The address presented on
the PCI bus is 0x41123450.
5. The next example shows an access to the fourth 16-Mbyte window.
The South AHB address is for the access is 0x4B123450. The address presented on
the PCI bus is 0x69123450.
6.4 Initializing the PCI Controller Configuration Registers
The PCI Base Address Registers along with any other pertinent PCI Configuration
Registers, located in the PCI Controller PCI Configuration Register space, must be
initialized by the Intel XScale processor when the IXP42X product line and IXC1100
control plane processors are configured as the PCI host. The PCI Base Address
Registers must be initialized by an external PCI device when the IXP42X product line
and IXC1100 control plane processors are configured as a PCI option.
The PCI Base Address Registers — along with any other registers in the PCI
Configuration Space — will be accessed by the Intel XScale processor using three
Configuration and Status Registers:
• PCI Configuration Port Address/Command/Byte Enables (PCI_CRP_AD_CBE)
Register
• PCI Configuration Port Write Data (PCI_CRP_WDATA) Register
• PCI Configuration Port Read Data (PCI_CRP_RDATA) Register.