Intel IXC1100, IXP42X 21.5 Register Descriptions

Intel® IXP42X product line and IXC1100 control plane processors—AHB Queue Manager (AQM)

Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor

DM September 2006

562 Order Number: 252480-006US

bus. Following each queue access where queue status is updated, status will be

transmitted on the Flag Bus, and only then. The Flag Bus Strobe(s) will be asserted

high for one clock cycle to indicate the presence of status on the Flag Bus.

Two processor interrupts will be provided, one for queues 0-31, aqm_int[0], and one

for queues 32-63, aqm_int[1]. Each of the interrupt signals is computed as a masked

32-way logical-OR of one edge-sensitive status bit per queue. In other words, each

queue contributes a single edge-sensitive input into one of the 32-way logical-OR

combinations. For queues 0-31, this input is independently configurable. It may be a

positive or negative edge-sensitive version of any one of the E, NE, NF or F status flag

bits. The selected status flag may be different for each queue. For queues 32-63, the

input is always the NE status flag bit with a positive edge-sensitive version only. The

set of selected 32 condition signals is masked by the corresponding interrupt enable

These interrupts are generated for active high, level triggered usage. On occurrence of

the selected transition of one or more of the status flag sources, an active high

interrupt level is registered. Via the AHB, the processor can read a 32-bit Interrupt

capability will be provided for each of the queue sources via writing a one to the

appropriate queue bit(s) within the interrupt register. Upon clearing (i.e. writing a ‘1’

to) the appropriate bit(s) in the Interrupt Register, the interrupt cannot be generated

again by the same source, until the active status flag condition is removed and then are

asserted again.

There is a bit in INT0SRCSELREG0 which will modify the reset operation of the

interrupts. If this bit is set to 0, then the interrupts will reset as described in the above

paragraph. If this bit is set to 1, then the interrupts will only reset if the interrupting

condition has also been cleared when the write the QUEINTREG occurs. In other words,

this bit determines if the interrupt is globally rising edge sensitive (INT0SCRSELREG0 is

‘0’) or is level sensitive (INT0SCRSELREG0 is ‘1’).

21.5 Register Descriptions

External agents wanting to access a queue, will perform an AHB read or write to the

Queue Access Register locations. As a result of the access to these locations, the AQM

will perform the requested access to the queue in SRAM. See Section 21.4.1 for

clarification on AHB queue accesses to the AQM. As described above, these queue

access registers are defined in a block of four 32-bit words, where only the first 32-bit

word is defined for a word size of one, only the first two 32-bit words are defined for a

word size of two and all four 32-bit words are defined for a word size of four.