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| Datasheet |
4.3.1 | Bus Mode Register (BUS_MODE) |
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| Offset: | 0000h | Size: | 32 bits |
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| This register establishes the bus operating modes for the DMAC. |
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| TYPE | DEFAULT |
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31:14 | RESERVED |
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| RO | - |
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13:8 | Programmable Burst Length (PBL) |
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| R/W | 001000b | |
| Indicates the maximum number of DWORDs to be transferred in one DMA |
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| transaction. This will be the maximum value that is used in a single block |
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| read/write. The DMAC will always attempt to burst transfer the length |
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| specified in the PBL each time it starts a burst transfer. |
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| PBL can be programmed with permissible values of 1, 2, 4, 8, 16 and 32. |
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| Any other value will result in undefined behavior. |
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7 | RESERVED |
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| RO | - |
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6:2 | Descriptor Skip Length (DSL) |
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| R/W | 00000b | |
| Specifies the number of DWORDs to skip between two unchained |
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| descriptors. |
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1 | Bus Arbitration (BAR) |
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| R/W | 0b |
| When this bit is set the RX DMA operations are given priority while |
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| guarantying TX at least one grant in between consecutive RX packets. |
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| When cleared, the arbitration ratio is dictated by the BUS_CFG[26:25] field. |
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0 | Software Reset (SRST) |
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| R/W/SC | 0b |
| When this bit is set, the DMAC and MAC are reset. This is a |
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| bit. |
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| Note: It will take up to 120ns for the SRST to complete |
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Revision 1.22 | 104 | SMSC LAN9420/LAN9420i |
| DATASHEET |
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