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Datasheet
| Receive Descriptor 3 (RDES3) | |
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| Table 3.8 RDES3 Bit Fields |
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BITS |
| DESCRIPTION |
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31:0 |
| Buffer 2 Address Pointer (Next Descriptor Address) |
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| The RCH (Second Address Chained) bit (RDES1[24]) determines the usage of this field as |
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| RCH is zero: This field contains the pointer to the address of buffer 2 in Host memory. The buffer |
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| must be DWORD |
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| DWORD aligned, the resulting behavior is undefined. |
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| RCH is one: Descriptor chaining is in use and this field contains the pointer to the next descriptor |
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| in Host memory. The descriptor must be |
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| the case where the buffer is not |
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| Note: If RER (RDES1[25]) is set, RCH is ignored and this field is treated as a pointer to buffer |
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| 2 as in the “RCH is zero” case above. |
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| Host Actions: Initializes this field. |
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| DMAC Actions: Reads this field upon opening a new DMA descriptor to obtain the buffer |
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| address. |
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3.4.2.2Transmit descriptors
The descriptors must be
TDES0 | OW |
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| RESERVED |
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| ES | RES | LC | NC | LT | EC | HF |
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| CC |
| ED | UE | DE | |||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 |
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| 4 | 3 | 2 | 1 | 0 | |
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TDES1 | IC | LS | FS | R | CK | AC | TE | TC | DP | R |
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| TBS2 |
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 |
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| 4 | 3 | 2 | 1 | 0 | |
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TDES2 |
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| BUFFER 1 ADDRESS POINTER |
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31 | 30 | 29 | 28 | 27 | 26 | 25 |
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| 4 | 3 | 2 | 1 | 0 | |
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TDES3 |
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| BUFFER 2 ADDRESS POINTER |
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 |
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| 4 | 3 | 2 | 1 | 0 |
Figure 3.17 Transmit Descriptor
SMSC LAN9420/LAN9420i | 45 | Revision 1.22 |
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