Datasheet
4.3.9Missed Frame and Buffer Overflow Counter Reg (MISS_FRAME_CNTR)Offset: | 0020h | Size: | 32 bits |
The DMAC maintains two counters to track the number of missed frames during a receive operation. The MISS_FRAME_CNTR register reports the current value of these counters and their overflow bits.
BITS | DESCRIPTION | TYPE | DEFAULT |
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31:29 | RESERVED | RO | - |
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28 | MIL RX FIFO Full Counter Overflow (MIL_OVER) | RC | 0b |
| Overflow bit for the MIL_FIFO_FULL counter. This bit is automatically |
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| cleared on a read. |
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27:17 | MIL RX FIFO Full Counter (MIL_FIFO_FULL) | RC | 000h |
| This field indicates the number of frames missed due a MIL RX FIFO full |
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| condition. This counter is automatically cleared on a read. |
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16 | RX Buffer Unavailable Counter Overflow (UNAV_OVER) | RC | 0b |
| Overflow bit for the RX_BUFF_UNAV counter. This bit is automatically |
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| cleared on a read. |
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15:0 | RX Buffer Unavailable Counter (RX_BUFF_UNAV) | RC | 0000h |
| This field indicates the number of frames missed due to receive buffers |
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| being unavailable. This counter is incremented each time the DMAC |
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| discards an incoming frame. This counter is automatically cleared on a |
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| read. |
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SMSC LAN9420/LAN9420i | 115 | Revision 1.22 |
| DATASHEET |
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