Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

Datasheet

BITS

 

DESCRIPTION

TYPE

DEFAULT

 

 

 

 

2

Receiver Enable (RXEN)

R/W

0b

 

When set (1), the MAC’s receiver is enabled and will receive frames from

 

 

 

the internal PHY. When reset, the MAC’s receiver is disabled and will not

 

 

 

receive any frames from the internal PHY.

 

 

 

Note:

In order to successfully enable the receive path, the RX DMAC

 

 

 

 

must be enabled by setting the Start/Stop Receive bit (SR) bit of

 

 

 

 

the DMA Controller Control (Operation Mode) Register

 

 

 

 

(DMAC_CONTROL) prior to enabling the receiver (by setting

 

 

 

 

RXEN).

 

 

 

Note:

In order to successfully disable the receive path, the receiver must

 

 

 

 

be disabled (by clearing RXEN) prior to disabling the RX DMAC

 

 

 

 

(by clearing the Start/Stop Receive bit (SR) bit of the DMA

 

 

 

 

Controller Control (Operation Mode) Register

 

 

 

 

(DMAC_CONTROL)). Otherwise, RX DMA will not stop

 

 

 

 

(DMAC_STATUS will continue to show the Receive Process State

 

 

 

 

(RS) as Running and Receive Process Stopped (RPS) does not

 

 

 

 

assert).

 

 

 

 

 

 

1-0

RESERVED

RO

-

 

 

 

 

 

Revision 1.22 (09-25-08)

122

SMSC LAN9420/LAN9420i

 

DATASHEET