SMSC LAN9420, LAN9420i 3.2.4.3PCI Target Interface Transaction Errors, 3.2.4.4PCI Discard Timer, 3.2.5Interrupt Gating Logic, Note:, BA + 3FCh, BA + 200h, BA + 1FCh, BA (BAR3)

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

Datasheet

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BA + 3FCh

CSR - Big Endian (512 Bytes)

BA + 200h

BA + 1FCh

CSR - Little Endian (512 Bytes)

BA (BAR3)

Figure 3.3 CSR Double Endian Mapping

3.2.4.2.2I/O MAPPING OF CSR

The I/O BAR (BAR4) is double mapped over the CSR space with the non-prefetchable area. The CSR big endian space is disabled, as the Host processors (Intel x86) that use the I/O BAR are little endian.

Note: A comparison of Figure 3.3 with Figure 3.4 indicates only the first 256 bytes of CSR little endian space is addressable via the I/O BAR.

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BA + 0FCh

CSR - Little Endian ( 256 Bytes)

BA (BAR4)

Figure 3.4 I/O Bar Mapping

I/O BAR and non- prefetchable memory are double mapped to the CSR space

3.2.4.3PCI Target Interface Transaction Errors

If the Host system attempts an unsupported cycle type when accessing the CSR via the PCI Target Interface, a slave transaction error will result and the PCI Target Interface will generate a Slave Bus Error Interrupt (SBERR_INT), if enabled. CSR may only be read or written as DWORD quantities and any other type of access is unsupported and will result in the assertion of SBERR_INT. Non-DWORD reads will return a DWORD while non-DWORD writes are silently discarded. In order to cleanly recover from this condition, a software reset or H/W reset must be performed. A software reset is accomplished by setting the SRST bit of the BUS_MODE register.

3.2.4.4PCI Discard Timer

When the PCI master performs a read of LAN9420/LAN9420i, the PCI Bridge will fetch the data and acknowledge the PCI transfer when data is available. If the PCI master malfunctions and does complete the transaction within 32768 PCI clocks, LAN9420/LAN9420i will flush the data to prevent a potential bus lock-up.

3.2.5Interrupt Gating Logic

One set of interrupts exists: PCI Host interrupts (PCI interrupts from LAN9420/LAN9420i to the PCI Host). PCI Host interrupts result from the assertion of the internal IRQ signal from the Interrupt Controller. Refer to Section 3.3.1, "Interrupt Controller," on page 28 for sources of this interrupt. Figure 3.5 illustrates how interrupts are sourced by the Interrupt Controller to the PCIB and are propagated to the Host. The Interrupt is passed on to the Host only when the Host has enabled it by setting bit 10 in the PCI Device Command Register. The Host may obtain interrupt status by reading

SMSC LAN9420/LAN9420i	27	Revision 1.22 (09-25-08)
	DATASHEET