Datasheet
Table 2.6 Power and Ground PinsNUM |
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| BUFFER |
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PINS | NAME | SYMBOL |
| TYPE | DESCRIPTION |
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| +3.3V | VDD33A |
| P | +3.3V Analog Power Supply |
2 | Analog |
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| Refer to the LAN9420/LAN9420i application note for |
Power |
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| Supply |
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| connection information. |
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| +1.8V PLL | VDD18PLL |
| P | +1.8V PLL Power Supply: This pin must be connected |
1 | Power |
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| to VDD18CORE for proper operation. |
Supply |
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| Refer to the LAN9420/LAN9420i application note for | |
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| |
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| additional connection information. |
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| +1.8V TX | VDD18TX |
| P | +1.8V Transmitter Power Supply: This pin must be |
1 | Power |
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| connected to VDD18CORE for proper operation. |
Supply |
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| Refer to the LAN9420/LAN9420i application note for | |
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| |
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| additional connection information. |
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| +3.3V | VDD33BIAS |
| P | +3.3V Master Bias Power Supply |
1 | Master Bias |
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| Refer to the LAN9420/LAN9420i application note for |
Power |
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| Supply |
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| additional connection information. |
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| +3.3V I/O | VDD33IO |
| P | +3.3V Power Supply for I/O Pins and Internal |
15 | Power |
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| Regulator |
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| |
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| Refer to the LAN9420/LAN9420i application note for |
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| additional connection information. |
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21 | Ground | VSS |
| P | Common Ground for I/O Pins, Core, and Analog |
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| Circuitry |
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| +1.8V Core | VDD18CORE |
| P | Digital Core +1.8V Power Supply Output from |
3 | Power |
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| Internal Regulator |
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| |
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| Refer to the LAN9420/LAN9420i application note for |
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| additional connection information. |
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| Table 2.7 | ||
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NUM |
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| BUFFER |
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PINS | NAME | SYMBOL |
| TYPE | DESCRIPTION |
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17 | No Connect | NC |
| - | No Connect: These pins must be left floating for |
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| normal device operation. |
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Revision 1.22 | 20 | SMSC LAN9420/LAN9420i |
| DATASHEET |
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