Datasheet
4.3.7DMA Controller Control (Operation Mode) Register (DMAC_CONTROL)Offset: | 0018h | Size: | 32 bits |
This register establishes the RX and TX operating modes and commands. This should be the last DCSR written as part of initialization.
BITS | DESCRIPTION | TYPE | DEFAULT |
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31:23 | RESERVED | RO | - |
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22 | RESERVED | R/W | 0b |
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21 | Must Be One (MBO) | R/W | 0b |
| This bit must be set to ‘1’ for normal device operation. |
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19:16 | RESERVED | RO | - |
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15:14 | RESERVED | R/W | 00b |
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13 | Start/Stop Transmission Command (ST) | R/W | 0b |
| When set, the transmission process is placed in the Running state, and the |
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| DMAC checks the transmit list at the current position for a frame to be |
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| transmitted. |
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| Descriptor acquisition is attempted either from the current position in the list, |
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| which is the transmit list base address set by TX_BASE_ADDR, or from the |
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| position retained when the transmit process was previously stopped. If no |
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| descriptor can be acquired, the transmit process enters the Suspended |
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| state. If the current descriptor is not owned by the DMA Controller, the |
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| transmission process enters the Suspended state and the Transmit Buffer |
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| Unavailable (DMAC_STATUS bit [2]) is set. The Start Transmission |
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| command is effective only when the transmission process is stopped. If the |
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| command is issued before setting the TX_BASE_ADDR, then the DMA |
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| Controller’s behavior will be undefined. |
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| When reset, the transmission process is placed in the Stopped state after |
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| completing the transmission of the current frame. The next descriptor |
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| position in the transmit list is saved, and becomes the current position when |
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| transmission is restarted. |
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| The Stop Transmission command is effective only when the transmission |
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| process is in either Running or Suspended state. |
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12:3 | RESERVED | RO | - |
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2 | Operate on Second Frame (OSF) | R/W | 0b |
| When set, this bit instructs the DMA Controller to process a second frame |
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| of transmit data even before status for the first frame is obtained. This bit |
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| affects the DMA Controller but not the MIL. |
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SMSC LAN9420/LAN9420i | 111 | Revision 1.22 |
| DATASHEET |
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