SMSC LAN9420, LAN9420i Chapter 7 Revision History, CORRECTION, SECTION/FIGURE/ENTRY, REVISION LEVEL & DATE, Table 7.1 Customer Revision History

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

Datasheet

Chapter 7 Revision History

Table 7.1 Customer Revision History

REVISION LEVEL & DATE	SECTION/FIGURE/ENTRY	CORRECTION
Rev. 1.22	Added PCI SIG certification logo to cover
(09-23-08)
Rev. 1.21	Figure 1.2	Fixed error: Changed “To option..” text to
(07-30-08)	LAN9420/LAN9420i Internal	“(optional)” and moved it to the end of the
	Block Diagram on page 11	descriptions.
	Figure 1.2	- Changed “To option..” text to “(optional)” and
	LAN9420/LAN9420i Internal	moved it to the end of the descriptions.
	Block Diagram on page 11	- Removed “To” from “To Ethernet”.
		- Placed bi-directional arrows on EEPROM,
		GPIO/LED, and PHY blocks.
	Section 4.5.5, "Auto	Changed bits 9 and 15 to RESERVED with a
	Negotiation Advertisement,"	default value of 0b.
	on page 140
	Table 4.10, “Standard PCI	Added note to default value of Revision ID stating
	Header Registers	that the default value is dependent on device
	Supported,” on page 150	revision.
	Table 4.10, “Standard PCI	Changed default values of Min_Gnt and Max_Lat
	Header Registers	to 02h and 04h, respectively.
	Supported,” on page 150
	Section 3.5.5.1, "RX	Changed last line of RX checksum calculation to
	Checksum Calculation," on	“checksum = [B1, B0] + C0 + [B3, B2] + C1 + …
	page 63	+ [0, BN] + CN-1”
	Section 3.5.4, "Wakeup	Added note: “When wake-up frame detection is
	Frame Detection," on	enabled via the WUEN bit of the Wakeup Control
	page 57, Section 4.4.1,	and Status Register (WUCSR), a broadcast wake-
	"MAC Control Register	up frame will wake-up the device despite the state
	(MAC_CR)," on page 119	of the Disable Broadcast (BCAST) bit in the MAC
		Control Register (MAC_CR). “
	Section 4.4.12, "Wakeup	Corrected GUE bit description to state: “....A global
	Control and Status Register	unicast frame has the MAC Address [0] bit set to
	(WUCSR)," on page 133	0.”
	Section 5.9, "Clock Circuit,"	Updated Drive Level from 0.5mW to 300uW.
	on page 166
	Section 4.5.5, "Auto	Fixed Pause Operation bit definitions to:
	Negotiation Advertisement,"	00 No PAUSE
	on page 140	01 Symmetric PAUSE
		10 Asymmetric PAUSE
		11 Advertise support for both symmetric PAUSE
		and Asymmetric PAUSE
		Added note stating: When both symmetric PAUSE
		and asymmetric PAUSE support are advertised
		(value of 11), the device will only be configured to,
		at most, one of the two settings upon auto-
		negotiation completion.

SMSC LAN9420/LAN9420i	169	Revision 1.22 (09-25-08)
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