Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

Datasheet

BITS

DESCRIPTION

TYPE

DEFAULT

 

 

 

 

14:10

RESERVED

RO

-

 

 

 

 

9

Receive Watchdog Timeout (RWT)

R/WC

0b

 

A Receive Watchdog Timeout occurs when the length of the receiving frame

 

 

 

is greater than 2048 bytes through 2560 bytes.

 

 

 

 

 

 

8

Receive Process Stopped (RPS)

R/WC

0b

 

Asserted when the Receive process enters the stopped state.

 

 

 

 

 

 

7

Receive Buffer Unavailable (RU)

R/WC

0b

 

Indicates that the next descriptor in the receive list is owned by the Host

 

 

 

and cannot be acquired by the DMA Controller. The reception process is

 

 

 

suspended. To resume processing receive descriptors, the Host should

 

 

 

change the ownership of the descriptor and issue a receive poll demand

 

 

 

command. If no receive poll demand is issued, the reception process

 

 

 

resumes when the next recognized incoming frame is received.

 

 

 

After the first assertion, RU is not asserted for any subsequent “not owned”

 

 

 

receive descriptor fetches. RU is set only when the previous receive

 

 

 

descriptor was owned by the DMA controller. RU remains asserted until it

 

 

 

is cleared by software.

 

 

 

 

 

 

6

Receive Interrupt (RI)

R/WC

0b

 

Indicates the completion of the frame reception. Specific frame status

 

 

 

information has been posted in the descriptor. The reception process

 

 

 

remains in the running state.

 

 

 

 

 

 

5:3

RESERVED

RO

-

 

 

 

 

2

Transmit Buffer Unavailable (TU)

R/WC

0b

 

Indicates that the next descriptor in the Transmit list is owned by the Host

 

 

 

system and cannot be acquired by the DMA Controller. The transmission

 

 

 

process is suspended (bits [22:20]). To resume processing transmit

 

 

 

descriptors, the Ownership bit in the descriptor should be set, indicating that

 

 

 

the DMA Controller now owns the buffer and then a transmit poll demand

 

 

 

command should be issued.

 

 

 

 

 

 

1

Transmit Process Stopped (TPS)

R/WC

0b

 

Set when the transmit process enters the stopped state.

 

 

 

 

 

 

0

Transmit Interrupt (TI)

R/WC

0b

 

Indicates that a frame transmission was completed and TDES1[31] is set in

 

 

 

the first Descriptor indicating that the TX descriptor has been updated.

 

 

 

 

 

 

Revision 1.22 (09-25-08)

110

SMSC LAN9420/LAN9420i

 

DATASHEET