SMSC LAN9420, LAN9420i 5.6PCI Clock Timing, MIN, TYP, MAX, Note, UNITS, PCICLK, SYMBOL, DATASHEET, DESCRIPTION, Figure 5.2 PCI Clock Timing, Table 5.9 PCI Clock Timing Values

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

Datasheet

5.6PCI Clock Timing

The following specifies the PCI clock requirements for LAN9420/LAN9420i:

		PCICLK
		tcyc
	thigh	tlow
	0.6*VDD33IO
	0.5*VDD33IO
	0.4*VDD33IO		0.4*VDD33IO p-to-p
				(minimum)
	0.3*VDD33IO
		0.2*VDD33IO
	Figure 5.2 PCI Clock Timing
	Table 5.9 PCI Clock Timing Values
SYMBOL	DESCRIPTION	MIN	TYP	MAX	UNITS
tcyc	PCICLK cycle time	30		∞	ns
thigh	PCICLK high time	11			ns
tlow	PCICLK low time	11			ns
-	PCICLK slew rate (Note 5.14)	1		4	V/ns

Note 5.14 This slew rate must be met across the minimum peak-to-peak portion of the clock waveform as shown in Figure 5.2.

Revision 1.22 (09-25-08)	162	SMSC LAN9420/LAN9420i
	DATASHEET