Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

Datasheet

BITS

DESCRIPTION

TYPE

DEFAULT

 

 

 

 

1

Wake Event Interrupt (WAKE_INT)

RO

0b

 

Indicates a valid MAC wakeup event (Wakeup Frame or Magic Packet) or

 

 

 

PHY interrupt (Energy-Detect) has been received. The particular source of

 

 

 

the interrupt can be determined by the WUPS field of the Power

 

 

 

Management Control Register (PMT_CTRL). Both WUPS bits must be

 

 

 

cleared in order to clear WAKE_INT. Writing to the WAKE_INT bit has no

 

 

 

effect.

 

 

 

 

 

 

0

DMAC Interrupt (DMAC_INT)

RO

0b

 

This interrupt is generated by the DMA controller. This bit is read-only. The

 

 

 

DMA interrupt is cleared by clearing the interrupt source in the

 

 

 

DMAC_STATUS DCSR. Writing to this bit has no effect.

 

 

 

 

 

 

Revision 1.22 (09-25-08)

90

SMSC LAN9420/LAN9420i

 

DATASHEET