Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

Datasheet

3.4.2.1Receive Descriptors

The receive descriptors must be 4-DWORD (16-byte) aligned. Except for the case where descriptor address chaining is disabled (RCH=0), there are no alignment restrictions on receive buffer addresses. Providing two buffers, two byte-count buffers, and two address pointers in each descriptor facilitates compatibility with various types of memory-management schemes. Figure 3.16 shows the receive descriptor.

RDES0

OW

FF

 

 

 

 

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RDES1

 

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BUFFER 1 ADDRESS POINTER

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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Figure 3.16 Receive Descriptor

 

Receive Descriptor 0 (RDES0)

 

RDES0 contains the received frame status, the frame length, and the descriptor ownership information.

 

 

Table 3.5 RDES0 Bit Fields

 

 

 

BITS

 

DESCRIPTION

 

 

 

31

 

OWN - Own Bit

 

 

When set, indicates that the descriptor block and associated buffer(s) are owned by the DMA

 

 

controller. When reset, indicates that the descriptor block and associated buffer(s) are owned by

 

 

the Host system.

 

 

Host Actions: Checks this bit to determine ownership of the descriptor block and associated

 

 

buffer(s). The Host sets this bit to pass ownership to the DMAC. The Host does not modify a

 

 

descriptor block or access its associated buffer(s) until this bit is cleared by DMAC or until the

 

 

DMAC is in STOPPED state, whichever comes first.

 

 

DMAC Actions: Reads this bit to determine ownership of the descriptor block and its associated

 

 

buffer(s). The DMAC clears this bit either when it completes the frame reception or when the

 

 

buffers that are associated with this descriptor are full. By clearing this bit, the DMAC closes the

 

 

descriptor block and passes ownership to the Host. If the DMAC fetches a descriptor with the

 

 

OWN bit cleared, the DMAC state machine enters the SUSPENDED state.

 

 

 

30

 

FF - Filter Fail

 

 

Indicates that the current frame failed the receive address filtering. This bit can only be set when

 

 

receive all (RXALL) is set in the MAC control register (MAC_CR). This bit is only valid when the

 

 

last descriptor (LS) bit is set and the received frame is greater than or equal to 64 bytes in length.

 

 

Host Actions: Checks this bit to determine status.

 

 

DMAC Actions: Sets/clears this bit to define status.

 

 

 

SMSC LAN9420/LAN9420i

41

Revision 1.22 (09-25-08)

 

DATASHEET