SMSC LAN9420, LAN9420i 1.8Control and Status Registers (CSR), 1.7.6Free Run Counter, 1.7.3EEPROM Controller, 1.7.4GPIO/LED Controller, 1.7.5General Purpose Timer

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

Datasheet

1.7.2PLL and Power Management

LAN9420/LAN9420i interfaces with a 25MHz crystal oscillator from which all internal clocks, with the exception of PCI clock, are generated. The internal clocks are all generated by the PLL and Power Management blocks. Various power savings modes exists that allow for the clocks to be shut down. These modes are defined by the power state of the PCI function. Please refer to Section 3.7, "Power Management," on page 73 for more information.

1.7.3EEPROM Controller

LAN9420/LAN9420i provides support for an optional EEPROM via the EEPROM Controller. Please refer to Section 3.3.5, "EEPROM Controller (EPC)," on page 31 for more information.

1.7.4GPIO/LED Controller

The 3-bit GPIO and 2-bit GPO (Multiplexed on the LED and EEPROM Pins) interface is managed by the GPIO/LED Controller. It is accessible via the System Control and Status Registers (SCSR). The GPIO signals can function as inputs, push-pull outputs and open drain outputs. The GPIOs can also be configured to trigger interrupts with programmable polarity. The GPOs are outputs only and have no means of generating interrupts.

Please refer to Section 4.2.5, "General Purpose Input/Output Configuration Register (GPIO_CFG)," on page 92 for more information.

1.7.5General Purpose Timer

The General Purpose Timer has no dedicated function within LAN9420/LAN9420i and may be programmed to issue a timed interrupt. Please refer to Section 3.3.3, "General Purpose Timer (GPT)," on page 30 for more information.

1.7.6Free Run Counter

The Free Run Counter has no dedicated function within LAN9420/LAN9420i and may be used by the software drivers as a timebase. Please refer to Section 3.3.4, "Free-Run Counter (FRC)," on page 31 for more information.

1.8Control and Status Registers (CSR)

LAN9420/LAN9420i’s functions are controlled and monitored by the Host via the Control and Status Registers (CSR). This register space includes registers that control and monitor the DMA controller (DMA Control and Status Registers - DCSR), the MAC (MAC Control and Status Registers - MCSR), the PHY (accessed indirectly through the MAC via the MII_ACCESS and MII_DATA registers), and the elements of the System Control Block via the System Control and Status Registers (SCSR). The CSR may be accessed be via I/O or memory operations. Big or Little Endian access is also configurable.

Revision 1.22 (09-25-08)	14	SMSC LAN9420/LAN9420i
	DATASHEET