Datasheet
Table 2.5 PLL and Ethernet PHY PinsNUM |
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| BUFFER |
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PINS | NAME | SYMBOL | TYPE | DESCRIPTION |
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| Crystal Input | XI | ICLK | Crystal Input: External 25MHz crystal input. This pin |
1 |
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| can also be driven by a |
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| When this method is used, XO should be left | |
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| |
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| unconnected. |
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1 | Crystal | XO | OCLK | Crystal Output: External 25MHz crystal output. |
Output |
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| Ethernet TX | TPO- | AIO | Ethernet Transmit Data Out Negative: The transmit |
1 | Data Out |
|
| data outputs may be swapped internally with receive |
| Negative |
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| data inputs when |
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| Ethernet TX | TPO+ | AIO | Ethernet Transmit Data Out Positive: The transmit |
1 | Data Out |
|
| data outputs may be swapped internally with receive |
| Positive |
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| data inputs when |
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| Ethernet RX | TPI- | AIO | Ethernet Receive Data In Negative: The receive data |
1 | Data In |
|
| inputs may be swapped internally with transmit data |
| Negative |
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| outputs when |
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| Ethernet RX | TPI+ | AIO | Ethernet Receive Data In Positive: The receive data |
1 | Data In |
|
| inputs may be swapped internally with transmit data |
| Positive |
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| outputs when |
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| External | EXRES | AI | External PHY Bias Resistor: Used for the internal |
1 | PHY Bias |
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| PHY bias circuits. Connect to an external 12.4K 1.0% |
| Resistor |
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| resistor to ground. |
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SMSC LAN9420/LAN9420i | 19 | Revision 1.22 |
| DATASHEET |
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