Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

Datasheet

 

Table 3.5 RDES0 Bit Fields (continued)

 

 

BITS

DESCRIPTION

 

 

7

TL - Frame Too Long

 

When set, indicates the frame length exceeds maximum Ethernet-specified size of 1518 bytes

 

(or 1522 bytes when VLAN tagging is enabled). This bit is valid only when last descriptor (LS) is

 

set. Frame too long is only a frame length indication and does not cause any frame truncation.

 

Host Actions: Checks this bit to determine status.

 

DMAC Actions: Sets/clears this bit to define status.

 

 

6

CS - Collision Seen

 

When set, this bit indicates that the frame has seen a collision after the collision window. This

 

indicates that a late collision has occurred.

 

Host Actions: Checks this bit to determine status.

 

DMAC Actions: Sets/clears this bit to define status.

 

 

5

FT - Frame Type

 

When set, indicates that the frame is an Ethernet-type frame (frame length field is greater than

 

or equal to 1536 bytes). When clear, indicates that the frame is an IEEE 802.3 frame. This bit is

 

not valid for runt frames of less than 14 bytes.

 

Host Actions: Checks this bit to determine status.

 

DMAC Actions: Sets/clears this bit to define status.

 

 

4

RW – Receive Watchdog

 

When set, indicates that the receive watchdog timer expired while receiving the current packet

 

with length greater than 2048 bytes through 2560 bytes.

 

Host Actions: Checks this bit to determine status.

 

DMAC Actions: Sets/clears this bit to define status.

 

 

3

ME - MII Error

 

When set, this bit indicates that a receive error was detected during frame reception (RX_ER

 

asserted on internal MII bus).

 

Host Actions: Checks this bit to determine status.

 

DMAC Actions: Sets/clears this bit to define status.

 

 

2

DB - Dribbling Bit

 

When set, indicates that the frame contained a noninteger multiple of 8 bits. This error is reported

 

only if the number of dribbling bits in the last byte is 4 in MII operating mode, or at least 3 in 10

 

Mb/s serial operating mode. This bit is not valid if collision seen (CS - RDES0[6]) is set. If set,

 

and the CRC error (CE - RDES0[1]) is reset, then the packet is valid.

 

Host Actions: Checks this bit to determine status.

 

DMAC Actions: Sets/clears this bit to define status.

 

 

1

CE - CRC Error

 

When set, indicates that a cyclic redundancy check (CRC) error occurred on the received frame.

 

This bit is also set when the MII error signal is asserted during the reception of a receive packet

 

even though the CRC may be correct. This bit is not valid if one of the following conditions exist:

 

„ The received frame is a runt frame

 

„ A collision occurred while the packet was being received

 

„ A watchdog timeout occurred while the packet was being received

 

Host Actions: Checks this bit to determine status.

 

DMAC Actions: Sets/clears this bit to define status.

 

 

0

RESERVED

 

Host Actions: Cleared on writes and ignored on reads.

 

DMAC Actions: Ignored on reads and cleared on writes.

 

 

SMSC LAN9420/LAN9420i

43

Revision 1.22 (09-25-08)

 

DATASHEET