SMSC LAN9420, LAN9420i 3.6.1.3NRZI and MLT3 Encoding, 3.6.1.4100M Transmit Driver, 3.6.1.5100M Phase Lock Loop (PLL), 3.6.2.1100M Receive Input

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

Datasheet

3.6.1.3NRZI and MLT3 Encoding

The scrambler block passes the 5-bit wide parallel data to the NRZI converter where it becomes a serial 125MHz NRZI data stream. The NRZI is encoded to MLT-3. MLT3 is a tri-level code where a change in the logic level represents a code bit “1” and the logic output remaining at the same level represents a code bit “0”.

3.6.1.4100M Transmit Driver

The MLT3 data is then passed to the analog transmitter, which launches the differential MLT-3 signal, on outputs TPO+ and TPO-, to the twisted pair media via a 1:1 ratio isolation transformer. The 10BASE-T and 100BASE-TX signals pass through the same transformer so that common “magnetics” can be used for both. The transmitter drives into the 100Ω impedance of the CAT-5 cable. Cable termination and impedance matching require external components.

3.6.1.5100M Phase Lock Loop (PLL)

The 100M PLL locks onto reference clock and generates the 125MHz clock used to drive the 125 MHz logic and the 100BASE-Tx Transmitter.

	RX_CLK			100M
				PLL
MAC
		Internal		MII		25MHz	4B/5B	25MHz by	Descrambler
MII 25MHz by 4 bits					by 4 bits		Decoder	5 bits	and SIPO
					125 Mbps Serial
NRZI			MLT-3				DSP: Timing
		NRZI			MLT-3		recovery, Equalizer
			Converter
Converter							and BLW Correction
A/D		MLT-3	Magnetics		MLT-3	RJ45	MLT-3	CAT-5
Converter

6 bit Data

Figure 3.26 Receive Data Path

3.6.2100BASE-TX Receive

The receive data path is shown in Figure 3.26. Detailed descriptions follow.

3.6.2.1100M Receive Input

The MLT-3 from the cable is fed into the PHY (on inputs TPI+ and TPI-) via a 1:1 ratio transformer. The ADC samples the incoming differential signal at a rate of 125M samples per second. Using a 64- level quanitizer it generates 6 digital bits to represent each sample. The DSP adjusts the gain of the ADC according to the observed signal levels such that the full dynamic range of the ADC can be used.

3.6.2.2Equalizer, Baseline Wander Correction and Clock and Data Recovery

The 6 bits from the ADC are fed into the DSP block. The equalizer in the DSP section compensates for phase and amplitude distortion caused by the physical channel consisting of magnetics, connectors,

SMSC LAN9420/LAN9420i	67	Revision 1.22 (09-25-08)
	DATASHEET