Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

Datasheet

Note 3.10 PHY register bits designated as NASR are not initialized by setting the PHY Soft Reset bit in the PHY’s Basic Control Register.

Note 3.11 PHY reset conditions and mode settings are discussed in Section 3.7.5.1, "PHY Resets," on page 80

3.7.5.1PHY Resets

In addition to the PHY_RST, PHY_SRST and PCInRST noted in Table 3.22, the PHY may also be reset on specific state transitions depending on the state of the VAUXDET signal and PME Enable (PME_EN) bit in the PCI Power Management Control and Status Register (PCI_PMCSR). Resets may leave the PHY in normal operating mode (all-capable with auto-negotiation enabled) or in the General Power-Down mode. Specific PHY reset conditions and the state of the PHY following reset, are detailed in Table 3.23 below. The state transitions noted in this table refer to those specified in Section 3.7.4, "Power States," on page 75.

Table 3.23 PHY Resets

CONDITION

VAUXDET

PME_EN

MODE

 

 

 

 

T9

0

X

Normal

 

 

 

 

T6

1

X

General Power-Down

 

 

 

 

T1, T3

X

0

General Power-Down

 

 

 

 

T10, T11

1

0

General Power-Down

 

 

 

 

T5 (D3RST)

X

0

Normal

 

 

 

 

3.7.6Detecting Power Management Events

LAN9420/LAN9420i supports the ability to generate PCI wake events using nPME on detection of a Magic Packet, Wakeup Frame or Ethernet link status change (energy detect). A simplified diagram of the wake event detection logic is shown in Figure 3.29.

WOL_EN

(PMT_CTRL Register)

RW

WAKE_INT

PME_EN(Interrupt Controller)

(PCI_PMCSR Register)

WUPS[1]

RW

 

(PMT_CTRL Register)

 

 

MAC Wakeup

 

nPME

Event

PME_STATUS

(PCI Bus)

 

 

(PCI_PMCSR Register)

 

ED_EN

(PMT_CTRL Register)

RW

WUPS[0]

(PMT_CTRL Register)

PHY Interrupt

Figure 3.29 Wake Event Detection Block Diagram

Revision 1.22 (09-25-08)

80

SMSC LAN9420/LAN9420i

 

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